DRAM

SMJ44400

Austin Semiconductor, Inc.

SMJ44400

Rev. 2.0 10/01

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

11

READ-WRITE CYCLE TIMING

NOTES:

1. Valid data is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an invalid-data state prior to the specified access tiems as the outputs are driven when

CAS\ and OE\ are low.

(1)