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MSC1213Y3 Datasheet(PDF) 5 Page - Texas Instruments |
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MSC1213Y3 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 105 page MSC1211, MSC1212 MSC1213,MSC1214 SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005 www.ti.com 5 ELECTRICAL CHARACTERISTICS: AVDD = 5V (continued) All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, AVDD = +5V, fMOD = 15.625kHz, PGA = 1, filter = Sinc3, Buffer ON, fDATA = 10Hz, Bipolar, fCLK = 8MHz, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise noted. For VDAC, VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF, unless otherwise noted. MSC1211/12/13/14 PARAMETER UNITS MAX TYP MIN CONDITIONS Analog Power-Supply Requirements Analog Power-Supply Voltage AVDD 4.75 5 5.25 V Analog Off Current(8) Analog OFF, PDCON = 48h < 1 nA PGA = 1, Buffer OFF 200 µA Analog ADC Current (IADC) PGA = 128, Buffer OFF 500 µA Analog Power-Supply ADC Current (IADC) PGA = 1, Buffer ON 240 µA Power-Supply Current PGA = 128, Buffer ON 850 µA Current VDAC Current (IVDAC) Excluding Load Current, External Reference 250 µA VREF Supply Current (IVREF) ADC ON, VDAC OFF 250 µA (1) The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64). (2) Calibration can minimize these errors. (3) The self gain calibration cannot have a REF IN+ of more than AV DD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF. (4) ∆VOUT is change in digital result. (5) 9pF switched capacitor at f SAMP clock frequency (see Figure 14). (6) Linearity calculated using a reduced code range of 512 to 65024; output unloaded. (7) Ensured by design and characterization; not production tested. (8) Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1). ELECTRICAL CHARACTERISTICS: AVDD = 3V All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, AVDD = +3V, fMOD = 15.625kHz, PGA = 1, filter = Sinc3, Buffer ON, fDATA = 10Hz, Bipolar, fCLK = 8MHz, and VREF ≡ (REF IN+) − (REF IN−) = +1.25V, unless otherwise noted. For VDAC, VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF, unless otherwise noted. MSC1211/12/13/14 PARAMETER CONDITIONS MIN TYP MAX UNITS Analog Inputs (AIN0−AIN7, AINCOM) Analog Input Range Buffer OFF AGND − 0.1 AVDD + 0.1 V Analog Input Range Buffer ON AGND + 50mV AVDD − 1.5 V Full-Scale Input Voltage Range (AIN+) − (AIN−) ±VREF/PGA V Differential Input Impedance Buffer OFF 7/PGA(1) M Ω Input Current Buffer ON 0.5 nA Fast Settling Filter −3dB 0.469 • fDATA Bandwidth Sinc2 Filter −3dB 0.318 • fDATA Bandwidth Sinc3 Filter −3dB 0.262 • fDATA Programmable Gain Amplifier User-Selectable Gain Range 1 128 Input Capacitance Buffer ON 9 pF Input Leakage Current Modulator OFF, T = +25 °C 0.5 pA Burnout Current Sources Sensor Input Open Circuit ±2 µA (1) The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64). (2) Calibration can minimize these errors. (3) The gain calibration cannot have a REF IN+ of more than AVDD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF. (4) ∆VOUT is change in digital result. (5) 9pF switched capacitor at fSAMP clock frequency (see Figure 14). (6) Linearity calculated using a reduced code range of 512 to 65024; output unloaded. (7) Ensured by design and characterization; not production tested. (8) Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1). |
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