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PL123E-05SI-R Datasheet(PDF) 3 Page - Micrel Semiconductor |
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PL123E-05SI-R Datasheet(HTML) 3 Page - Micrel Semiconductor |
3 / 10 page (Preliminary) PL123E-05 Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 3 LAYOUT RECOMMENDATIONS The following guidelines are to assist y ou with a performance optimized PCB design: Signal Integrity and Termination Considerations - Keep traces short! - Trace = Inductor. With a capacitive load this equals ringing! - Long trace = Transmission Line. Without proper termination this will cause reflections ( looks like ringing ). - Design long traces as “striplines” or “microstrips” with defined impedance. - Match trace at one side to avoid reflections bounc- ing back and forth. Decoupling and Power Supply Considerations - Place decoupling capacitors as close as possible to the VDD pin(s) to limit noise from the power supply - Addition of a ferrite bead in series with VDD can help prevent noise from other board sources - Value of decoupling capacitor is frequency de- pendant. Typical values to use are 0.1 F for de- signs using frequencies < 50MHz and 0.01 F for designs using frequencies > 50MHz. Typical CMOS termination Place Series Resistor as close as possible to CMOS output CMOS Output Buffer ( Typical buffer impedance 20 To CMOS Input 50 line Connect a 33 series resistor at each of the output clocks to enhance the stability of the output signal |
Similar Part No. - PL123E-05SI-R |
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