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PL123E-09HOC-R Datasheet(PDF) 2 Page - Micrel Semiconductor |
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PL123E-09HOC-R Datasheet(HTML) 2 Page - Micrel Semiconductor |
2 / 10 page (Preliminary) PL123E-09 Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 2 PIN DESCRIPTIONS Name Package Type Type Description TSSOP-16L SOP-16L REF[1] 1 1 I Input reference frequency. CLKA1[2] 2 2 O Buffered clock output, Bank A CLKA2[2] 3 3 O Buffered clock output, Bank A VDD 4,13 4,13 P VDD connection GND 5,12 5,12 P GND connection CLKB1[2] 6 6 O Buffered clock output, Bank B CLKB2[2] 7 7 O Buffered clock output, Bank B S2[3] 8 8 I Selector input S1[3] 9 9 I Selector input CLKB3[2] 10 10 O Buffered clock output, Bank B CLKB4[2] 11 11 O Buffered clock output, Bank B CLKA3[2] 14 14 O Buffered clock output, Bank A CLKA4[2] 15 15 O Buffered clock output, Bank A CLKOUT[2] 16 16 O Buffered clock output. Internal feedback on this pin. Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs. 3: Weak Pull-Up on S1 and S2 SELECTOR DEFINITION S2 S1 CLOCK A1–A4 (Bank A) CLOCK B1–B4 (Bank B) CLKOUT Output Source PLL Shutdown 0 0 Three-state Three-state Driven PLL N 0 1 Driven Three-state Driven PLL N 1 0 Driven Driven Driven Reference Y 1 1 Driven Driven Driven PLL N INPUT / OUTPUT SKEW CONTROL The PL123E-09 will achieve Zero Delay from input to output when all the outputs are loaded equally . Adjust- ments to the input/output delay can be made by adding additional loading to the CLKOUT pin. Please contact Micrel for more information. |
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