Microstepping DMOS Driver with Translator

A5976

3

Allegro MicroSystems, LLC

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Terminal List Table

Number

Name

Description

1

SENSE1

Sense resistor for bridge 1

2

FAULTn

Open-drain logic output

3

DIR

Logic input

4

OUT1A

DMOS full-bridge 1, output A

5

PFD

Analog input for mixed-decay setting

6

RC1

Analog input for fixed off-time, bridge 1

7

AGND*

Analog ground

8

REF

Gm reference input

9

RC2

Analog input for fixed off-time, bridge 2

10

VDD

Logic supply voltage

11

OUT2A

DMOS full-bridge 2, output A

12

MS2

Logic input

13

MS1

Logic input

14

SENSE2

Sense resistor for bridge 2

15

VBB2

Load supply for bridge 2

16

DECAY

Logic input

17

RESETn

Logic input

18

OUT2B

DMOS full-bridge 2, output B

19

STEP

Logic input

20

VREG

Regulator decoupling

21

PGND*

Power ground

22

VCP

Reservoir capacitor

23

CP1

Charge pump capacitor

24

CP2

Charge pump capacitor

25

OUT1B

DMOS full-bridge 1, output B

26

ENABLEn

Logic input

27

SLEEPn

Logic input

28

VBB1

Load supply for bridge 1

–

PAD*

Thermal pad

* GND, PGND, and thermal pad must be connected together externally under the device.

SENSE1

FAULTn

DIR

OUT1A

PFD

RC1

AGND

REF

RC2

VDD

OUT2A

MS2

MS1

SENSE2

VBB1

SLEEPn

ENABLEn

OUT1B

CP2

CP1

VCP

PGND

VREG

STEP

OUT2B

RESETn

DECAY

VBB2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

PAD

PINOUT DIAGRAM AND TERMINAL LIST TABLE

Package LP,

28-Pin TSSOP