SC16C654IB64 datasheet(10/52 Pages) PHILIPS

Part #	SC16C654IB64

Description	Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder

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Manufacturer	PHILIPS [NXP Semiconductors]

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10 / 52 page

Philips Semiconductors

SC16C654/654D

Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder

Product data

Rev. 04 — 19 June 2003

10 of 52

9397 750 11617

RTSA, RTSB,

RTSC, RTSD

14, 22,

48, 56

5, 13,

36, 44

O

Request to Send (Active-LOW). These outputs are associated with individual

UART channels, A through D. A logic 0 on the RTS pin indicates the transmitter

has data ready and waiting to send. Writing a logic 1 in the modem control

register MCR[1] will set this pin to a logic 0, indicating data is available. After a

reset this pin will be set to a logic 1. This pin only affects the transmit and

receive operations when Auto RTS function is enabled via the Enhanced

Feature Register (EFR[6]) for hardware ﬂow control operation.

R/W18

-

I

Read/Write strobe. This function is associated with the 68 mode only. This pin

provides the combined functions for Read or Write strobes.

Logic 1 = Read from UART register selected by CS and A0-A4.

Logic0=Write to UART register selected by CS and A0-A4.

RXA, RXB,

RXC, RXD

7, 29,

41, 63

62, 20,

29, 51

I

Receive data input RXA-RXD. These inputs are associated with individual

serial channel data to the SC16C654/654D. The RX signal will be a logic 1

during reset, idle (no data), or when the transmitter is disabled. During the local

loop-back mode, the RX input pin is disabled and TX data is connected to the

UART RX input internally.

RXRDY38

-

O

Receive Ready (Active-LOW). This function is associated with 68-pin package

only. RXRDY contains the wire-ORed status of all four receive channel FIFOs,

RXRDYA-RXRDYD. A logic 0 indicates receive data ready status, i.e., the RHR

is full, or the FIFO has one or more RX characters available for unloading. This

pin goes to a logic 1 when the FIFO/RHR is empty, or when there are no more

characters available in either the FIFO or RHR. Individual channel RX status is

read by examining individual internal registers via CS and A0-A4 pin functions.

TXA, TXB,

TXC, TXD

17, 19,

51, 53

8, 10,

39, 41

O

Transmit data A, B, C, D. These outputs are associated with individual serial

transmit channel data from the SC16C654/654D. The TX signal will be a logic 1

during reset, idle (no data), or when the transmitter is disabled. During the local

loop-back mode, the TX output pin is disabled and TX data is internally

connected to the UART RX input.

TXRDY39

-

O

Transmit Ready (Active-LOW). This function is associated with the 68-pin

package only. TXRDY contains the wire-ORed status of all four transmit

channel FIFOs, TXRDYA-TXRDYD. A logic 0 indicates a buffer ready status,

i.e., at least one location is empty and available in one of the TX channels

(A-D). This pin goes to a logic 1 when all four channels have no more empty

locations in the TX FIFO or THR. Individual channel TX status can be read by

examining individual internal registers via CS and A0-A4 pin functions.

VCC

13, 47,

64

4, 21,

35, 52

I

Power supply inputs.

XTAL1

35

25

I

Crystal or external clock input. Functions as a crystal input or as an external

clock input. A crystal can be connected between this pin and XTAL2 to form an

internal oscillator circuit (see Figure 6). Alternatively, an external clock can be

connected to this pin to provide custom data rates. (See Section 6.11

“Programmable baud rate generator”.)

XTAL2

36

26

O

Output of the crystal oscillator or buffered clock. (See also XTAL1.) Crystal

oscillator output or buffered clock output.

Table 2:

Pin description…continued

Symbol

Type

Description

PLCC68 LQFP64

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