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MC100LVE310 Datasheet(PDF) 1 Page - ON Semiconductor |
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MC100LVE310 Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 7 page © Semiconductor Components Industries, LLC, 2016 July, 2016 − Rev. 6 1 Publication Order Number: MC100LVE310/D MC100LVE310 3.3 V ECL 2:8 Differential Fanout Buffer Description The MC100LVE310 is a low voltage, low skew 2:8 differential ECL fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The LVE310 offers two selectable clock inputs to allow for redundant or test clocks to be incorporated into the system clock trees. To ensure that the tight skew specification is met it is necessary that both sides of the differential output are terminated into 50 W, even if only one side is being used. In most applications all eight differential pairs will be used and therefore terminated. In the case where fewer than eight pairs are used it is necessary to terminate at least the output pairs adjacent to the output pair being used in order to maintain minimum skew. Failure to follow this guideline will result in small degradations of propagation delay (on the order of 10−20 ps) of the outputs being used, while not catastrophic to most designs this will result in an increase in skew. Note that the package corners isolate outputs from one another such that the guideline expressed above holds only for outputs on the same side of the package. The MC100LVE310, as with most ECL devices, can be operated from a positive VCC supply in LVPECL mode. This allows the LVE310 to be used for high performance clock distribution in +3.3 V systems. Designers can take advantage of the LVE310’s performance to distribute low skew clocks across the backplane or the board. In a PECL environment series or Thevenin line terminations are typically used as they require no additional power supplies, if parallel termination is desired a terminating voltage of VCC − 2.0 V will need to be provided. For more information on using PECL, designers should refer to Application Note AN1406/D. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. Features • 200 ps Part-to-Part Skew • 50 ps Output-to-Output Skew • PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −3.8 V • Q Output will Default LOW with All Inputs Open or at VEE • The 100 Series Contains Temperature Compensation • These Devices are Pb-Free, Halogen Free and are RoHS Compliant PLCC−28 FN SUFFIX CASE 776 MARKING DIAGRAM* A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb-Free Package MC100LVE310G AWLYYWW 1 www.onsemi.com *For additional marking information, refer to Application Note AND8002/D. Device Package Shipping† ORDERING INFORMATION MC100LVE310FNG PLCC−28 (Pb-Free) 37 Units / Tube MC100LVE310FNR2G PLCC−28 (Pb-Free) 500 Tape & Reel †For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. |
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