MC100EP196

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3

Table 1. PIN DESCRIPTION

Pin

Name

I/O

Default State

Description

23, 25, 26, 27,

29, 30, 31, 32,

1, 2

D[0:9]

LVCMOS, LVTTL,

ECL Input

LOW

Single−ended Parallel Data Inputs [0:9]. Internal 75 k

(Note 1)

3

D[10]

LVCMOS, LVTTL,

ECL Input

LOW

Single−ended CASCADE/CASCADE Control Input. Internal 75 k

W

4

IN

ECL Input

LOW

Noninverted Differential Input. Internal 75 k

5

IN

ECL Input

HIGH

Inverted Differential Input. Internal 75 k

6

−

−

ECL Reference Voltage Output

7

−

−

Reference Voltage for ECL Mode Connection

8

−

−

LVCMOS, ECL, OR LVTTL Input Mode Select

9, 28

−

−

ted to Power Supply to Guarantee Proper Operation. (Note 2)

13, 18, 19, 22

−

−

ted to Power Supply to Guarantee Proper Operation. (Note 2)

10

LEN

ECL Input

LOW

Single−ended D pins LOAD / HOLD input. Internal 75 k

11

SETMIN

ECL Input

LOW

Single−ended Minimum Delay Set Logic Input. Internal 75 k

W to

12

SETMAX

ECL Input

LOW

Single−ended Maximum Delay Set Logic Input. Internal 75 k

W to

14

CASCADE

ECL Output

−

Inverted Differential Cascade Output for D[10] Input. Typically Ter-

minated with 50

15

CASCADE

ECL Output

−

Noninverted Differential Cascade Output for D[10] Input. Typically

Terminated with 50

16

EN

ECL Input

LOW

Single−ended Output Enable Pin. Internal 75 k

17

FTUNE

Analog Input

−

Fine Tuning Input.

21

Q

ECL Output

−

Noninverted Differential Output. Typically Terminated with 50

W to

20

Q

ECL Output

−

Inverted Differential Output. Typically Terminated with 50

W to

1. SETMIN will override SETMAX if both are high. SETMAX and SETMIN will override all D[0:10] inputs.