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DSC400-4234Q0001KE2T Datasheet(PDF) 9 Page - Microchip Technology |
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DSC400-4234Q0001KE2T Datasheet(HTML) 9 Page - Microchip Technology |
9 / 20 page 2016 Microchip Technology Inc. DS20005612A-page 9 DSC400 4.4 LVCMOS FIGURE 4-4: Typical LVCMOS Termination Scheme. RS is a series resistor implemented to match the trace impedance to that of the clock output. Depending on the board layout, the value may range from 0Ω to 27Ω. Note 1: See the Output Waveform section for more information. 2: The addition of IDDCORE and IDDIO provides the total current consumption of the device. TABLE 4-4: LVCMOS OUTPUTS Parameter Symbol Min. Typ. Max. Units Condition Output Logic Levels VOH 0.9 x VDD — — V Output Logic High, I = ±6 mA VOL — — 0.1 x VDD Output Logic Low, I = ±6 mA Output Transition Time (Note 1) tR — 1.1 2.0 ns Rise Time, 20% to 80%, CL= 15 pF tF — 1.3 2.0 Fall Time, 20% to 80%, CL= 15 pF Frequency f0 2.3 — 170 MHz All Temperature Ranges, Except Automotive — — 100 Automotive Temperature Range Output Duty Cycle SYM 44 — 55 % — IO Supply Current (Note 2) IDDIO — 11 14 mA Per Output at 125 MHz, CL = 15 pF Period Jitter JPER —3— psRMS CLK(0:3) = 125 MHz Integrated Phase Noise JPH —0.3 — psRMS 200 kHz to 20 MHz @ 125 MHz — 0.38 — 100 kHz to 20 MHz @ 125 MHz — 1.7 2.0 12 kHz to 20 MHz @125 MHz 50 Ω RS |
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