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MCF5232 Datasheet(PDF) 3 Page - Freescale Semiconductor, Inc |
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MCF5232 Datasheet(HTML) 3 Page - Freescale Semiconductor, Inc |
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3 / 44 page  ColdFire MCF523x and eTPU Advantages and Features DC Motor with Speed and Current Closed Loops, Driven by eTPU on MCF523x, Rev. 0 Freescale Semiconductor 3 • eTPU with 16 or 32 channels, 6 Kbytes of code memory, and 1.5 Kbytes of data memory with eTPU debug support • 64 Kbytes of internal SRAM • External bus speed of half the CPU operating frequency (75 MHz bus @ 150 MHz core) • 10/100 Mbps bus-mastering Ethernet controller • 8 Kbytes of configurable instruction/data cache • Three universal asynchronous receiver/transmitters (UARTs) with DMA support • Controller area network 2.0B (FlexCAN module) — Optional second FlexCAN module multiplexed with the third UART • Inter-integrated circuit (I2C) bus controller • Queued serial peripheral interface (QSPI) module • Hardware cryptography accelerator (optional) — Random number generator — DES/3DES/AES block cipher engine — MD5/SHA-1/HMAC accelerator • 4-channel, 32-bit direct memory access (DMA) controller • 4-channel, 32-bit input capture/output compare timers with optional DMA support • 4-channel, 16-bit periodic interrupt timers (PITs) • Programmable software watchdog timer • Interrupt controller capable of handling up to 126 interrupt sources • Clock module with phase locked loop (PLL) • External bus interface module including a 2-bank synchronous DRAM controller • 32-bit, non-multiplexed bus with up to 8 chip select signals that support page-mode FLASH memories For more information, refer to Reference 1. 1.2 eTPU Module The eTPU is an intelligent, semi-autonomous co-processor designed for timing control, I/O handling, serial communications, motor control, and engine control applications. It operates in parallel with the host CPU. The eTPU processes instructions and real-time input events, performs output waveform generation, and accesses shared data without the host CPU’s intervention. Consequently, the host CPU setup and service times for each timer event are minimized or eliminated. The eTPU has up to 32 timer channels, in addition to having 6 Kbytes of code memory and 1.5 Kbytes of data memory that store software modules downloaded at boot time, and can be mixed and matched as needed for any application. The eTPU provides more specialized timer processing than the host CPU can achieve. This is partially due to the eTPU implementation, which includes specific instructions for handling and processing time events. |
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