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SA8027W Datasheet(PDF) 11 Page - NXP Semiconductors |
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SA8027W Datasheet(HTML) 11 Page - NXP Semiconductors |
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11 / 22 page  Philips Semiconductors Product data SA8027 2.5 GHz low voltage, low power RF fractional-N/IF integer frequency synthesizer 2001 Aug 21 11 1.7 Charge Pumps The PHP and PHI charge pumps are driven by the main phase detector, while the PHA charge pump is driven by the auxiliary phase detector. The ISET value (refer to Table 1) is determined by the external resistor attached to the RSET pin. The charge pump, by default, will automatically go into speed-up mode (which can deliver up to 15*ISET for PHP_SU, and 36*ISET for PHI), based on the strobe pulse width following the A word, to reduce switching speed for large tuning voltage steps (i.e., large frequency steps). Figure 10 shows the recommended passive loop filter configuration. Note: This charge pump architecture eliminates the need for added active switches and reduces external component count. Furthermore, the programmable charge pump gains provide some programmability to the loop filter bandwidth. The duration of speed-up mode is determined by the strobe pulse width following the A word. Recommended optimal strobe width is equal to the total loop filter capacitance charge time from state 1 to state 2. The strobe width must not exceed this charge time. The strobe width is controlled by the CPU ( × number of clock cycles). In addition, charge pumps will stay in speed-up mode continuously while Tspu = 1 (in D word). The speed-up mode can also be disabled by programming Tdis-spu = 1 (in D word). SR02356 VCO C3 C2 R2 C1 R1 PHP[PHP–SU] PHI Figure 10. Typical passive 3-pole loop filter Table 1. Main and auxiliary charge pump currents CP1 CP0 IPHA IPHP IPHP–SU IPHI 0 0 1.5xlSET 3xISET 15xlSET 36xlSET 0 1 0.5xlSET 1xlSET 5xlSET 12xlSET 1 0 1.5xlSET 3xlSET 15xlSET 0 1 1 0.5xlSET 1xlSET 5xlSET 0 NOTES: 1. ISET = VSET/RSET: bias current for charge pumps. 2. CP1 is used to disable the PHI pump, IPHP–SU is the total current at pin PHP during speed up condition. 1.8 Lock Detect The output LOCK maintains a logic ‘1’ when the auxiliary phase detector (AND/ORed) with the main phase detector indicates a lock condition. The lock condition for the main and auxiliary synthesizers is defined as a phase difference of less than "1 period of the frequency at the input REFin+, –. One counter can fulfill the lock condition when the other counter is powered down. Out of lock (logic ‘0’) is indicated when both counters are powered down. 1.9 Power-down mode The power-down signal can be either hardware (PON) or software (PD). The PON signal is exclusively ORed with the PD bits in B-word. If PON = 0, then the part is powered up when PD = 1. PON can be used to invert the polarity of the software bit PD. When the synthesizer is reactivated after power-down, the main and reference dividers are synchronized to avoid possibility of random phase errors on power-up. |
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