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SN74LVC2G126-EP Datasheet(PDF) 1 Page - Texas Instruments |
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SN74LVC2G126-EP Datasheet(HTML) 1 Page - Texas Instruments |
1 / 13 page 3 6 1Y 2Y 8 1 V CC 1OE 5 GND 4 2A 2 7 2OE 1A SN74LVC2G126-EP www.ti.com SCES856 – DECEMBER 2013 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS Check for Samples: SN74LVC2G126-EP 1 FEATURES • Supports 5-V VCC Operation SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS • Inputs Accept Voltages to 5.5 V • Controlled Baseline • Max tpd of 6.8 ns at 3.3 V • One Assembly and Test Site • Low Power Consumption, 10- μA Max ICC • One Fabrication Site • ±24-mA Output Drive at 3.3 V • Available in Military (–55°C to 125°C) • Typical VOLP (Output Ground Bounce) Temperature Range <0.8 V at VCC = 3.3 V, TA = 25°C • Extended Product Life Cycle • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C • Extended Product-Change Notification • Ioff Supports Partial-Power-Down Mode • Product Traceability Operation • Latch-Up Performance Exceeds 100 mA Per DCU PACKAGE (TOP VIEW) JESD 78, Class II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DESCRIPTION This dual bus buffer gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC2G126 is a dual bus driver/line driver with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION(1) TJ PACKAGE(2) ORDERABLE PART NUMBER TOP-SIDE MARKING VID NUMBER –55°C to 125°C VSSOP - DCU Tape of 250 CLVC2G126MDCUTEP CEPR V62/14604-01XE (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. (2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Function Table (Each Buffer) INPUTS OUTPUT Y OE A H H H H L L L X Z 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2013, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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