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SM320VC5507-EP Datasheet(PDF) 2 Page - Texas Instruments |
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SM320VC5507-EP Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 109 page  SM320VC5507-EP SPRS613 – SEPTEMBER 2009 www.ti.com Contents 1 Features ............................................................................................................................. 9 1.1 SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS ......................................... 9 2 Introduction ...................................................................................................................... 10 2.1 Description ................................................................................................................. 10 2.2 Pin Assignments ........................................................................................................... 11 2.3 Signal Descriptions ........................................................................................................ 13 3 Functional Overview .......................................................................................................... 23 3.1 Functional Block Diagram ................................................................................................ 23 3.2 Memory ..................................................................................................................... 24 3.2.1 On-Chip Dual-Access RAM (DARAM) ....................................................................... 24 3.2.2 On-Chip Single-Access RAM (SARAM) ..................................................................... 24 3.2.3 On-Chip Read-Only Memory (ROM) ......................................................................... 24 3.2.4 Memory Maps ................................................................................................... 25 3.2.4.1 PGE Package Memory Map ...................................................................... 25 3.2.5 Boot Configuration .............................................................................................. 26 3.3 Peripherals ................................................................................................................. 26 3.4 Direct Memory Access (DMA) Controller ............................................................................... 27 3.4.1 DMA Channel Control Register (DMA_CCR) ............................................................... 27 3.5 I 2C Interface ................................................................................................................ 28 3.6 Configurable External Buses ............................................................................................. 28 3.6.1 External Bus Selection Register (EBSR) .................................................................... 29 3.6.2 Parallel Port ..................................................................................................... 30 3.6.3 Parallel Port Signal Routing ................................................................................... 31 3.7 General-Purpose Input/Output (GPIO) Ports .......................................................................... 33 3.7.1 Dedicated General-Purpose I/O .............................................................................. 33 3.7.2 Address Bus General-Purpose I/O ........................................................................... 34 3.7.3 EHPI General-Purpose I/O .................................................................................... 36 3.8 System Register ........................................................................................................... 37 3.9 USB Clock Generation .................................................................................................... 38 3.10 Memory-Mapped Registers .............................................................................................. 40 3.11 Peripheral Register Description .......................................................................................... 42 3.12 Interrupts .................................................................................................................... 52 3.12.1 IFR and IER Registers ......................................................................................... 53 3.12.2 Interrupt Timing ................................................................................................. 55 3.12.3 Waking Up From IDLE Condition ............................................................................. 55 3.12.3.1 Waking Up From IDLE With Oscillator Disabled ............................................... 55 3.12.4 Idling Clock Domain When External Parallel Bus Operating in EHPI Mode ............................ 55 4 Support ............................................................................................................................ 56 4.1 Notices Concerning JTAG (IEEE 1149.1) Boundary Scan Test Capability ........................................ 56 4.1.1 Initialization Requirements for Boundary Scan Test ....................................................... 56 4.1.2 Boundary Scan Description Language (BSDL) Model ..................................................... 56 4.2 Documentation Support ................................................................................................... 56 4.3 TMS320VC5507 Device Nomenclature ................................................................................ 57 5 Electrical Specifications ..................................................................................................... 58 5.1 ABSOLUTE MAXIMUM RATINGS ...................................................................................... 58 5.2 RECOMMENDED OPERATING CONDITIONS ....................................................................... 59 2 Contents Copyright © 2009, Texas Instruments Incorporated |
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