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OMAP-L138 Datasheet(PDF) 2 Page - Texas Instruments

Part # OMAP-L138
Description  OMAP-L138 C6000 DSP ARM Processor
Download  286 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

OMAP-L138 Datasheet(HTML) 2 Page - Texas Instruments

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OMAP-L138
SPRS586I – JUNE 2009 – REVISED SEPTEMBER 2014
www.ti.com
16-Bit mDDR SDRAM with 256-MB Address
– IEEE 802.3 Compliant
Space
– MII Media-Independent Interface
• Three Configurable 16550-Type UART Modules:
– RMII Reduced Media-Independent Interface
– With Modem Control Signals
– Management Data I/O (MDIO) Module
– 16-Byte FIFO
• Video Port Interface (VPIF):
– 16x or 13x Oversampling Option
– Two 8-Bit SD (BT.656), Single 16-Bit or Single
• LCD Controller
Raw (8-, 10-, and 12-Bit) Video Capture
Channels
• Two Serial Peripheral Interfaces (SPIs) Each with
Multiple Chip Selects
– Two 8-Bit SD (BT.656), Single 16-Bit Video
Display Channels
• Two Multimedia Card (MMC)/Secure Digital (SD)
Card Interfaces with Secure Data I/O (SDIO)
• Universal Parallel Port (uPP):
Interfaces
– High-Speed Parallel Interface to FPGAs and
• Two Master and Slave Inter-Integrated Circuits
Data Converters
( I2C Bus™)
– Data Width on Both Channels is 8- to 16-Bit
• One Host-Port Interface (HPI) with 16-Bit-Wide
Inclusive
Muxed Address and Data Bus For High Bandwidth
– Single-Data Rate or Dual-Data Rate Transfers
• Programmable Real-Time Unit Subsystem
– Supports Multiple Interfaces with START,
(PRUSS)
ENABLE, and WAIT Controls
– Two Independent Programmable Real-Time Unit
• Serial ATA (SATA) Controller:
(PRU) Cores
– Supports SATA I (1.5 Gbps) and SATA II
32-Bit Load-Store RISC Architecture
(3.0 Gbps)
4KB of Instruction RAM Per Core
– Supports All SATA Power-Management
Features
512 Bytes of Data RAM Per Core
– Hardware-Assisted Native Command Queueing
PRUSS can be Disabled via Software to
(NCQ) for up to 32 Entries
Save Power
– Supports Port Multiplier and Command-Based
Register 30 of Each PRU is Exported From
Switching
the Subsystem in Addition to the Normal R31
Output of the PRU Cores.
• Real-Time Clock (RTC) with 32-kHz Oscillator and
Separate Power Rail
– Standard Power-Management Mechanism
• Three 64-Bit General-Purpose Timers (Each
Clock Gating
Configurable as Two 32-Bit Timers)
Entire Subsystem Under a Single PSC Clock
• One 64-Bit General-Purpose or Watchdog Timer
Gating Domain
(Configurable as Two 32-Bit General-Purpose
– Dedicated Interrupt Controller
Timers)
– Dedicated Switched Central Resource
• Two Enhanced High-Resolution Pulse Width
• USB 1.1 OHCI (Host) with Integrated PHY (USB1)
Modulators (eHRPWMs):
• USB 2.0 OTG Port with Integrated PHY (USB0)
– Dedicated 16-Bit Time-Base Counter with
– USB 2.0 High- and Full-Speed Client
Period and Frequency Control
– USB 2.0 High-, Full-, and Low-Speed Host
– 6 Single-Edge Outputs, 6 Dual-Edge Symmetric
– End Point 0 (Control)
Outputs, or 3 Dual-Edge Asymmetric Outputs
– End Points 1,2,3,4 (Control, Bulk, Interrupt, or
– Dead-Band Generation
ISOC) RX and TX
– PWM Chopping by High-Frequency Carrier
• One Multichannel Audio Serial Port (McASP):
– Trip Zone Input
– Two Clock Zones and 16 Serial Data Pins
• Three 32-Bit Enhanced Capture (eCAP) Modules:
– Supports TDM, I2S, and Similar Formats
– Configurable as 3 Capture Inputs or 3 Auxiliary
– DIT-Capable
Pulse Width Modulator (APWM) Outputs
– FIFO Buffers for Transmit and Receive
– Single-Shot Capture of up to Four Event Time-
• Two Multichannel Buffered Serial Ports (McBSPs):
Stamps
– Supports TDM, I2S, and Similar Formats
• Packages:
– AC97 Audio Codec Interface
– 361-Ball Pb-Free Plastic Ball Grid Array (PBGA)
– Telecom Interfaces (ST-Bus, H100)
[ZCE Suffix], 0.65-mm Ball Pitch
– 128-Channel TDM
– 361-Ball Pb-Free PBGA [ZWT Suffix],
0.80-mm Ball Pitch
– FIFO Buffers for Transmit and Receive
• Commercial, Extended, or Industrial Temperature
• 10/100 Mbps Ethernet MAC (EMAC):
2
OMAP-L138 C6000 DSP+ARM Processor
Copyright © 2009–2014, Texas Instruments Incorporated
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Product Folder Links: OMAP-L138


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