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OMAP3503DZCBCS Datasheet(PDF) 6 Page - Texas Instruments |
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OMAP3503DZCBCS Datasheet(HTML) 6 Page - Texas Instruments |
6 / 329 page 64 64 Async 64 64 L2$ 256K MPU Subsystem ARM Cortex- A8 TM Core 16K/16K L1$ 32 Channel System DMA 32 32 Parallel TV Amp LCD Panel CVBS or S-Video Dual Output 3-Layer Display Processor (1xGraphics, 2xVideo) Temporal Dithering SDTV→QCIF Support 32 Camera ISP Image Capture Hardware Image Pipeline and Preview Camera (Parallel) 64 HS USB Host (with USB TTL) HS USB OTG 32 L3 Interconnect Network-Hierarchial, Performance, and Power Driven 64K On-Chip RAM 2KB Public/ 62KB Secure 32 112K On-Chip ROM 80KB Secure/ 32KB BOOT 32 SMS: SDRAM Memory Scheduler/ Rotation 64 SDRC: SDRAM Memory Controller L4 Interconnect 32 System Controls PRCM 2xSmartReflex TM Control Module External Peripherals Interfaces Peripherals: 3xUART, 3xHigh-Speed I2C, 5xMcBSP (2x with Sidetone/Audio Buffer) 4xMcSPI, 6xGPIO, 3xHigh-Speed MMC/SDIO, HDQ/1 Wire, 2xMailboxes 12xGPTimers, 2xWDT, 32K Sync Timer GPMC: General Purpose Memory Controller NAND/ NOR Flash, SRAM 32 Emulation Debug: SDTI, ETM, JTAG, Coresight TM DAP External and Stacked Memories 32 OMAP Applications Processor OMAP3503-HiRel SPRS663 – FEBRUARY 2010 www.ti.com 1.3 Functional Block Diagram Figure 1-1 shows the functional block diagram of the OMAP3503 Applications Processor. Figure 1-1. OMAP3503 Functional Block Diagram 6 OMAP3503-HiRel Applications Processor Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): OMAP3503-HiRel |
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