Vcc (x5)

MUX

MUXout

Phase

Comp

GND

(x3)

Fin

Fin*

û

Compensation

(24 bit)

N Divider

(18 bit)

OSCin

R Divider

(16 bit)

Lock

Detect

Charge

Pump

CPout

MICROWIRE

Interface

CLK

LE

DATA

CE

GND/OSCin*

MOD

Modulation

Generator

TRIG1

TRIG2

2X

Vcp

4/5

Prescaler

Copyright © 2016, Texas Instruments Incorporated

7

LMX2491

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SNAS711 – OCTOBER 2016

Product Folder Links: LMX2491

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Copyright © 2016, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The LMX2491 is a microwave PLL, consisting of a reference input and divider, high frequency input and divider,

charge pump, ramp generator, and other digital logic. The Vcc power supply pins run at a nominal 3.3 volts,

while the charge pump supply pin, Vcp, operates anywhere from Vcc to 5 volts. The device is designed to

operate with an external loop filter and VCO. Modulation is achieved by manipulating the MASH engine.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 OSCin Input

The reference can be applied in several ways. If using a differential input, this must be terminated differentially

with a 100-Ω resistance and AC-coupled to the OSCin and GND/OSCin* terminals. If driving this single-ended,

then the GND/OSCin* terminal may be grounded, although better performance is attained by connecting the

GND/OSCin* terminal through a series resistance and capacitance to ground to match the OSCin terminal

impedance.

7.3.2 OSCin Doubler

The OSCin doubler allows the input signal to the OSCin to be doubled to have higher phase detector

frequencies. This works by clocking on both the rising and falling edges of the input signal, so it therefore

requires a 50% input duty cycle.

7.3.3 R Divider

The R counter is 16 bits divides the OSCin signal from 1 to 65535. If DIFF_R = 0, then any value can be chosen

in this range. If DIFF_R=1, then the divide is restricted to 2,4,8, and 16, but allows for higher OSCin frequencies.

7.3.4 PLL N Divider

The 16-bit N divider divides the signal at the Fin terminal down to the phase detector frequency. It contains a 4/5

prescaler that creates minimum divide restrictions, but allows the N value to increment in values of one.

Table 1. Allowable Minimum N Divide for Delta Sigma

Modulation Order

MODULATOR ORDER

MINIMUM N DIVIDE

Integer Mode, 1st-Order Modulator

16

2nd-Order Modulator

17

3rd-Order Modulator

19

4th-Order Modulator

25