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DLP6500BFYE Datasheet(PDF) 5 Page - Texas Instruments |
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DLP6500BFYE Datasheet(HTML) 5 Page - Texas Instruments |
5 / 50 page 5 DLP6500 www.ti.com DLPS040A – OCTOBER 2014 – REVISED OCTOBER 2016 Product Folder Links: DLP6500 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Pin Functions (continued) PIN(1) TYPE (I/O/P) SIGNAL DATA RATE(2) INTERNAL TERM(3) DESCRIPTION TRACE (mils)(4) NAME NO. D_BN(8) AA29 Input LVDS DDR Differential Data, Negative 555.9 D_BN(9) Y28 Input LVDS DDR Differential Data, Negative 555.42 D_BN(10) W27 Input LVDS DDR Differential Data, Negative 556.26 D_BN(11) V26 Input LVDS DDR Differential Data, Negative 555.52 D_BN(12) T30 Input LVDS DDR Differential Data, Negative 556 D_BN(13) R29 Input LVDS DDR Differential Data, Negative 557.17 D_BN(14) R27 Input LVDS DDR Differential Data, Negative 555.25 D_BN(15) N27 Input LVDS DDR Differential Data, Negative 555.19 D_BP(0) AB12 Input LVDS DDR Differential Data, Positive 551.93 D_BP(1) AC11 Input LVDS DDR Differential Data, Positive 557.1 D_BP(2) Y14 Input LVDS DDR Differential Data, Positive 544.38 D_BP(3) AA15 Input LVDS DDR Differential Data, Positive 555.98 D_BP(4) AB16 Input LVDS DDR Differential Data, Positive 555.56 D_BP(5) AC19 Input LVDS DDR Differential Data, Positive 547.17 D_BP(6) AC23 Input LVDS DDR Differential Data, Positive 556.47 D_BP(7) Y20 Input LVDS DDR Differential Data, Positive 543.25 D_BP(8) AC29 Input LVDS DDR Differential Data, Positive 555.71 D_BP(9) AB28 Input LVDS DDR Differential Data, Positive 556.32 D_BP(10) AA27 Input LVDS DDR Differential Data, Positive 555.35 D_BP(11) Y26 Input LVDS DDR Differential Data, Positive 555.65 D_BP(12) U29 Input LVDS DDR Differential Data, Positive 555.28 D_BP(13) T28 Input LVDS DDR Differential Data, Positive 557.25 D_BP(14) P28 Input LVDS DDR Differential Data, Positive 555.83 D_BP(15) P26 Input LVDS DDR Differential Data, Positive 556.67 SERIAL CONTROL SCTRL_AN C21 Input LVDS DDR Differential Serial Control, Negative 555.14 SCTRL_BN AA21 Input LVDS DDR Differential Serial Control, Negative 555.14 SCTRL_AP C23 Input LVDS DDR Differential Serial Control, Positive 555.13 SCTRL_BP AA23 Input LVDS DDR Differential Serial Control, Positive 555.13 CLOCKS DCLK_AN B22 Input LVDS Differential Clock Negative 555.12 DCLK_BN AB22 Input LVDS Differential Clock Negative 555.12 DCLK_AP B24 Input LVDS Differential Clock Positive 555.13 DCLK_BP AB24 Input LVDS Differential Clock Positive 555.12 SERIAL COMMUNICATIONS PORT (SCP) SCP_DO B2 Output LVCMOS SDR Serial Communications Port Output 525.78 SCP_DI F4 Input LVCMOS SDR Pull-Down Serial Communications Port Data Input 509.96 SCP_CLK E3 Input LVCMOS Pull-Down Serial Communications Port Clock 403.93 SCP_ENZ D4 Input LVCMOS Pull-Down Active-low Serial Communications Port Enable 464.17 MICROMIRROR RESET CONTROL RESET_ADDR(0) C5 Input LVCMOS Pull-Down Reset Driver Address Select 1088.3 RESET_ADDR(1) E5 Input LVCMOS Pull-Down Reset Driver Address Select 979.26 RESET_ADDR(2) G5 Input LVCMOS Pull-Down Reset Driver Address Select 900.45 RESET_ADDR(3) AC3 Input LVCMOS Pull-Down Reset Driver Address Select 658.56 RESET_MODE(0) D8 Input LVCMOS Pull-Down Reset Driver Mode Select 1012.52 RESET_MODE(1) C11 Input LVCMOS Pull-Down Reset Driver Mode Select 789.83 RESET_SEL(0) T4 Input LVCMOS Pull-Down Reset Driver Level Select 539.64 RESET_SEL(1) U5 Input LVCMOS Pull-Down Reset Driver Level Select 400.3 RESET_STROBE V2 Input LVCMOS Pull-Down Reset Address, Mode, & Level latched on rising-edge 446.34 |
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