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BD906xx-C series

TSZ02201-0T1T0AL00130-1-2

© 2014 ROHM Co., Ltd. All rights reserved.

www.rohm.com

TSZ22111・15・001

15.Sep.2015 Rev.005

Description of Blocks

1.

ERROR_AMP

The ERROR_AMP block is an error amplifier and its inputs are the reference voltage 0.8 V (Typ) and the

“FB” pin

voltage. (Refer to recommended examples on p.16 to 17). The output

“VC” pin controls the switching duty, the output

voltage is set by

“FB” pin with external resistors. Moreover, the external resistor and capacitor are required to COMP pin

as phase compensation circuit (Refer to phase compensation selection method on p.17 to 18).

2.

SOFT_START

increasing the input of the error amplifier when the power supply turns ON, which also results to the gradual increase of

The soft start time is changed by setting of the switching frequency. (Refer to p.18)

3.

EN / SYNC

The IC is in normal operation when the voltage on the “EN / SYNC” pin is more than 2.6 V. The IC is shut down when the

voltage on the “EN / SYNC” pin is less than 0.8 V. Furthermore, external synchronization is possible when external clock

are

applied to the “EN / SYNC” pin. The switching frequency range of the external synchronization is within ±20 % of the

switching frequency and is limited by the external resistance connected to the RT pin.

kHz.

4.

OSC (Oscillator)

This circuit generates the clock pulses that are input to SLOPE block. The switching frequency is determined by the

current going through the external resistor RT at constant voltage of ca. 0.8V. The switching frequency can be set in the

range between 50 kHz to 600 kHz (Refer to p.16 Figure 13). The output of the OSC block send clock signals to

PWM_LATCH. Moreover the generated pulses of the OSC block are also used as clock of the counter of SS and

SCP_LATCH blocks.

5.

SLOPE

This block generates saw tooth waves using the clock generated by the OSC block. The generated saw tooth waves are

combined with the current sense and sent to the CUR_COMP.

6.

CUR_COMP (Current Comparator)

The CUR_COMP block compares the signals between the ERROR_AMP and the combined signals from the SLOPE

block and current sense. The output signals are sent to the PWM_LATCH block.

7.

PWM_LATCH

The PWM_LATCH block is a LATCH circuit. The OSC block output (set) and CUR_COMP block output (reset) are the

inputs of this block. The PWM_LATCH block outputs PWM signals.

8.

TSD (Thermal Shut down)

The TSD block prevents thermal destruction / thermal runaway of the IC by turning OFF the Pch POWER MOSFET

output when the temperature of the chip reaches more than about 175 °C (Typ). When the chip temperature falls to a

specified level, the switching will resume. However, since the TSD is designed to protect the IC, the chip temperature

should be provided with the thermal shutdown detection temperature of less than approximately Tjmax = 150 °C.

9.

OCP (Over Current Protection)

OCP is activated when the voltage between the drain and source (on-resistance × load current) of the Pch POWER

MOSFET when it is ON, exceeds the reference voltage which is internally set within the IC. This OCP is a self-return

type. When OCP is activated, the ON duty will be small, and the output voltage will decrease. However, this protection

circuit is only effective in preventing destruction from sudden accident. It does not support the continuous operation of

the protection circuit (e.g. if a load, which significantly exceeds the output current capacitance, is connected).

10. SCP (Short Circuit Protection) and SCP-LATCH

While OCP is activated, and if the output voltage falls below 70 %, SCP will be activated. When SCP is active, the output

will be turned OFF after a period of 1024 pulse. It extends the time that the output is OFF to reduce the average output

current. In addition, during startup of the IC, this feature is masked until it reaches a certain output voltage to prevent the

startup failure.

11. UVLO (Under Voltage Lock-Out)

UVLO is a protection circuit that prevents low voltage malfunction. It prevents malfunction of the internal circuit from

will be restarted. This threshold voltage and release voltage have a hysteresis of 280 mV (Typ).

12. DRV (Driver)

This circuit drives the gate electrode of the Pch POWER MOSFET output. It reduces the increase of the Pch POWER

MOSFET’s on-resistance by switching the driving voltage when the power supply voltage drop.