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LM41 Datasheet(PDF) 11 Page - National Semiconductor (TI) |
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LM41 Datasheet(HTML) 11 Page - National Semiconductor (TI) |
11 / 27 page 1.0 Functional Description (Continued) Signal labels that begin with the label Slv_ depict the drive by the LM41. All other signals show what would be seen when probing SWD for a particular function (e.g. "Master Wr 0" is the Master transmitting a Data Bit with the value of 0). 1.2.1 Bus Inactive The bus is inactive when the SWD signal is high for a period of at least t INACT. The bus is inactive between each "bit signal". 1.2.2 Data Bit 0 and 1 All Data Bit signal transfers are started by the master. A Data Bit 0 is indicated by a "short" pulse; a Data Bit 1 is indicated by a longer pulse. The direction of the bit is relative to the master, as follows: • Data Write - a Data Bit transferred from the master to the LM41. • Data Read - a Data Bit transferred from the LM41 to the master. A master must monitor the bus as inactive before starting a Data Bit (Read or Write). A master initiates a data write by driving the bus active (low level) for the period that matches the data value (t Mtr0 or tMtr1 for a write of "0" or "1", respectively). The LM41 will detect that the SWD becomes active within a period of t SFEdet, and will start measuring the duration that the SWD is active in order to detect the data value. A master initiates a data read by driving the bus for a period of t Mtr0. The LM41 will detect that the SWD becomes active within a period of t SFEdet. For a data read of "0", the LM41 will not drive the SWD. For a data read of "1" the LM41 will start within t SFEdet to drive the SWD low for a period of t SLout1. Both master and LM41 must monitor the time at which the bus becomes inactive to identify a data read of "0" or "1". During each Data Bit, both the master and all the LM41s must monitor the bus (the master for Attention Request and Reset; the LM41s for Start Bit, Attention Request and Reset) by measuring the time SWD is active (low). If a Start Bit, Attention Requests or Reset "bit signal" is detected, the current "bit signal" is not treated as a Data Bit. Note that the bit rate of the protocol varies depending on the data transferred. Thus, the LM41 has a value of "0" in reserved or unused register bits for bus bandwidth efficiency. 1.2.3 Start Bit A master must monitor the bus as inactive before beginning a Start Bit. The master uses a Start Bit to indicate the beginning of a transfer. LM41s will monitor for Start Bits all the time, to allow synchronization of transactions with the master. If a Start Bit occurs in the middle of a transaction, the LM41 being ad- dressed will abort the current transaction. In this case the transaction is not "completed" by the LM41 (see Section 1.3 "SensorPath Bus Transactions"). During each Start Bit, both the master and all the LM41s must monitor the bus for Attention Request and Reset, by measuring the time SWD is active (low). If an Attention Request or Reset condition is detected, the current "bit signal" is not treated as a Start Bit. The master may attempt to send the Start Bit at a later time. 1.2.4 Attention Request The LM41 may initiate an Attention Request when the Sen- sorPath bus is inactive. Note that a Data Bit, or Start Bit, from the master may start simultaneously with an Attention Request from the LM41. In addition, two LM41s may start an Attention Request simul- taneously. Due to its length, the Attention Request has pri- ority over any other "bit signal", except Reset. Conflict with Data Bits and Start Bits are detected by all the devices, to allow the bits to be ignored and re-issued by their originator. The LM41 will either check to see that the bus is inactive before starting an Attention Request, or start the Attention Request within the t SFEdet time interval after SWD becomes active. The LM41 will drive the signal low for t SLoutA time. After this, both the master and the LM41 must monitor the bus for a Reset Condition. If a Reset condition is detected, the current "bit signal" is not treated as an Attention Request. After Reset, an Attention Request can not be sent before the master has sent 14 Data Bits on the bus. See Section 1.3.5 for further details on Attention Request generation. 1.2.5 Bus Reset The LM41 issues a Reset at power up. The master must also generate a Bus Reset at power-up for at least the minimum reset time, it must not rely on the LM41. SensorPath puts no limitation on the maximum reset time of the master. Follow- ing a Bus Reset, the LM41 may generate an Attention Re- quest only after the master has sent 14 Data Bits on the bus. See Section 1.3.5 for further details on Attention Request generation. 1.3 SensorPath BUS TRANSACTIONS SensorPath is designed to work with a single master and up to seven slave devices. Each slave has a unique address. The LM41 supports up to 2 device addresses that are se- lected by the state of the address pin ADD. The Register Set of the LM41 is defined in Section 2.0. 1.3.1 Bus Reset Operation A Bus Reset Operation is global on the bus and affects only the communication interface of all the devices connected to it. The Bus Reset operation does not affect either the con- tents of the device registers, or device operation, to the extent defined in LM41 Register Set, see Section 2.0. The Bus Reset operation is performed by generating a Reset signal on the bus. The master must apply Reset after power- up, and before it starts operation. The Reset signal end will be monitored by all the LM41s on the bus. After the Reset Signal the SensorPath specification requires that the master send a sequence of 8 Data Bits with a value of "0", without a preceding Start Bit. This is required to enable slaves that "train" their clocks to the bit timing. The LM41 does not require nor does it support clock training. www.national.com 11 |
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