© Semiconductor Components Industries, LLC, 2014

June, 2014 − Rev. 19

1

Publication Order Number:

MC10EP195/D

MC10EP195, MC100EP195

3.3V ECL Programmable

Delay Chip

The MC10/100EP195 is a Programmable Delay Chip (PDC)

designed primarily for clock deskewing and timing adjustment. It

provides variable delay of a differential NECL/PECL input transition.

The delay section consists of a programmable matrix of gates and

multiplexers as shown in the logic diagram, Figure 3. The delay

increment of the EP195 has a digitally selectable resolution of about

10 ps and a net range of up to 10.2 ns. The required delay is selected by

the 10 data select inputs D[9:0] values and controlled by the LEN

(pin 10). A LOW level on LEN allows a transparent LOAD mode of

real time delay values by D[9:0]. A LOW to HIGH transition on LEN

will LOCK and HOLD current values present against any subsequent

changes in D[10:0]. The approximate delay values for varying tap

numbers correlating to D0 (LSB) through D9 (MSB) are shown in

Table 6 and Figure 4.

Because the EP195 is designed using a chain of multiplexers it has a

fixed minimum delay of 2.2 ns. An additional pin D10 is provided for

controlling Pins 14 and 15, CASCADE and CASCADE, also latched

by LEN, in cascading multiple PDCs for increased programmable

range. The cascade logic allows full control of multiple PDCs.

Switching devices from all “1” states on D[0:9] with SETMAX LOW

to all “0” states on D[0:9] with SETMAX HIGH will increase the

delay equivalent to “D0”, the minimum increment.

Select input pins D[10:0] may be threshold controlled by

for LVCMOS, ECL, or LVTTL level signals. For LVCMOS input

W resistor

this device only. For single−ended input conditions, the unused

mF capacitor and limit current sourcing or sinking

The 100 Series contains temperature compensation.

Low

Inputs

32

1

LQFP−32

FA SUFFIX

CASE 873A

MARKING

DIAGRAM*

XXX

= 10 or 100

A

= Assembly Location

WL, L

= Wafer Lot

YY, Y

= Year

WW, W = Work Week

G or

G = Pb−Free Package

*For additional marking information, refer to

Application Note AND8002/D.

MCXXX

EP195

AWLYYWWG

http://onsemi.com

See detailed ordering and shipping information in the package

dimensions section on page 17 of this data sheet.

ORDERING INFORMATION

QFN32

MN SUFFIX

CASE 488AM

32

1

MCXXX

EP195

AWLYYWW

G

G

1

(Note: Microdot may be in either location)