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IDT5V9910A-7SO Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT5V9910A-7SO Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 6 page 2 COMMERCIALANDINDUSTRIALTEMPERATURERANGES IDT5V9910A 3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR. PIN CONFIGURATION NOTE: 1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute- maximum-rated conditions for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS(1) Symbol Description Max Unit Supply Voltage to Ground –0.5 to +7 V VI DC Input Voltage –0.5 to VCC+0.5 V REF Input Voltage –0.5 to +5.5 V Maximum Power Dissipation (TA = 85°C) 530 mW TSTG Storage Temperature –65 to +150 ° C NOTE: 1. Capacitance applies to all inputs except TEST and FS. It is characterized but not production tested. CAPACITANCE(TA =+25°C,f= 1MHz,VIN=0V) Parameter Description Typ. Max. Unit CIN InputCapacitance 5 7 pF PIN DESCRIPTION Pin Name Type Description REF I N Reference Clock Input FB I N FeedbackInput TEST(1) I N When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Set LOW for normal operation. GND/ sOE(1) I N Synchronous Output Enable. When HIGH, it stops clock outputs (except Q2 and Q3) in a LOW state - Q2 and Q3 may be used as the feedback signal to maintain phase lock. Set GND/ sOE LOW for normal operation. VCCQ/PE I N Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference clock. FS(2) I N Frequency range select: FS = GND: 15 to 35MHz FS = MID (or open): 25 to 60MHz FS = VCC: 40 to 85MHz Q0 - Q7 OUT Eight clock output VCCN PWR Power supply for output buffers VCCQ PWR Power supply for phase locked loop and other internal circuitry GND PWR Ground SOIC TOP VIEW NOTES: 1. When TEST = MID and GND/ sOE = HIGH, PLL remains active. 2. This input is wired to Vcc, GND, or unconnected. Default is MID level. If it is switched in the real time mode, the outputs may glitch, and the PLL may require an additional lock time before all data sheet limits are achieved. 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 REF FS NC VCCQ /P E Q0 Q1 GN D Q2 Q3 GN D TE ST NC G ND/sO E Q7 Q6 GN D Q5 Q4 FB VCCN VCCN V CC Q V CCN V CCN |
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