10-Tap Silicon Delay Line

_____________________________________________________________________

3

Note 1: All voltages are referenced to ground.

Note 2: Measured with outputs open.

Note 4: Temperature and voltage tolerances are with respect to the actual delay measured over stated temperature range and a 4.75V

to 5.25V range.

Note 5: Intermediate delay values are available on a custom basis.

Note 6: See Test Conditions section.

Note 7: All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if tap 1 slows down, all other

taps also slow down; tap 3 can never be faster than tap 2.

Note 8: Pulse width and period specifications may be exceeded; however, accuracy is application sensitive (decoupling, layout, etc.)

Note 9: For Tap 1 delays greater than 20ns, the tolerance is ±3ns or ±5%, whichever is greater.

CAPACITANCE

Typical Operating Characteristics

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Input Capacitance

510

pF

47

48

49

50

51

52

53

54

46

DS1110-50 TAP 10 DELAY

vs. TEMPERATURE

TEMPERATURE (

°C)

60

35

10

-15

-40

85

DS1110-500 TAP 10 DELAY

vs. TEMPERATURE

TEMPERATURE (

°C)

60

35

10

-15

450

475

500

525

550

575

425

-40

85

500kHz INPUT

10

1.0

20

40

60

80

100

120

140

160

180

200

0

0.1

100

DS1110-50 ACTIVE CURRENT

vs. INPUT FREQUENCY

FREQUENCY (MHz)

15pF LOAD/TAP

DS1110-500 ACTIVE CURRENT

vs. INPUT FREQUENCY

FREQUENCY (MHz)

1.0

5

10

15

20

25

30

35

40

0

0.1

10

15pF LOAD/TAP