05 | Keysight | M9203A PXIe High-Speed Digitizer/Wideband Digital Receiver - Data Sheet

Firmware Options

The M9203A PXIe High-Speed Digitizer/Wideband Digital

Receiver provides several firmware options:

– DGT: Digitizer firmware

– INT: Interleaved channel sampling functionality

– DDC: Wideband real-time digital down-conversion

Easy firmware switch

A simple call to the configuration function will enable to switch to

the required option.

DGT digitizer firmware

The digitizer firmware:

– Allows standard data acquisition, including: digitizer

initialization, setting of the acquisition and clocking modes,

management of channel triggering for best synchronization,

storing data in the internal memory and/or transferring them

through the backplane bus.

– Implements multi-record acquisition functionality.

– Supports fixed internal clocking frequency with internal or

external reference, and variable frequency external clock.

– Offers programmable binary decimation to lower the sample

for single record.

e.g. you can select from 1.6 GS/s down to 1.5625 MS/s.

– Trigger time interpolator (TTI): high precision integrated time

to digital converter can be used to increase time measure-

ment accuracy.

INT interleaved channel sampling functionality

This interleave option allows two channels to be combined and to

reach 3.2 GS/s in one channel acquisition mode.

FDK custom firmware capability

1. A calibration digitizer function is available with each firmware.

2. Only available with DGT option.

3. Please contact Keysight to find out the repetition rate that can be

achieved in your application.

4. On the Virtex-6 LX195T DPU FPGA.

5. There are 11 W maximum power dedicated to FPGA processing, the

custom firmware design must fit within this power provision.

The triggered simultaneous acquisition and readout architecture

allows to continuously acquire new records while reading previ-

ous ones.

TSR solution is dedicated to applications requiring no trigger loss,

achieving longer recording time when compares with standard

digitizer (-DGT).

TSR option main features:

– High trigger rate with guaranteed no lost trigger for specific

– Easy to use solution, implementing an optimal and

automated control of memory addressing.

– Selecting larger memory size option allows longer record

size and provides larger buffer for data transfer to host PC,

especially useful for applications with non-periodic trigger or

very high trigger rate during a limited period.

DDC real-time digital down-conversion

The real-time digital down-conversion option (-DDC), in addition

to the basic digitizer functionality, implements a real-time digital

decimation and filtering on the digitized data, allowing the user

to tune and zoom on the signals of interest. This exclusive IP

algorithm provides very powerful and flexible digital down-

conversion on 2 channels. The filters and local oscillators (LO) are

synchronized to maintain constant phase and timing relationships

allowing phase-coherent post processing.

The DDC provides three main functions:

– Frequency shifting (tune): Independently shifting each chan-

nels IF signal into baseband, allows the analysis bandwidth

to be set around the signal of interest.

– Data reduction (zoom): Reducing the bandwidth and sample

rate to match the analyzed signal decreases the amount of

data that needs to be transferred for a given capture dura-

tion, in turn accelerating post-processing operations.

– Magnitude trigger: Setting the magnitude level that the

down converted signal needs to achieve at a specified

frequency and bandwidth to generate a digital trigger on all

channels.

These functions allow isolation of the signal of interest from

other signals in a crowded spectrum, improved dynamic range

as the integrated noise is reduced, and increased SNR and

effective number of bits (ENOB). The resulting advantage for your

application is a reduced test time, while improving overall test

efficiency.

TSR triggered simultaneous acquisition and readout