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ML7125-001 Datasheet(PDF) 5 Page - LAPIS Semiconductor Co., Ltd. |
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ML7125-001 Datasheet(HTML) 5 Page - LAPIS Semiconductor Co., Ltd. |
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5 / 33 page  FEDL7125-04 ML7125-001/ML7125-002 5/33 E2 SPICLK TM4 Input I --- SPICLK : SPI SLAVE Clock TM4 : Test mode definition input UART pins No Pin Name ML7125-001 Pin Name ML7125-002 Status in reset I/O Active Level Function B1 UART_TXD *1 High output O2 --- UART TXD output C1 UART_RXD *1 input B2pd --- UART RXD input *1: Same as ML7125-001 I2C pins No Pin Name ML7125-001 Pin Name ML7125-002 Status in reset I/O Active Level Function B2 I2C_SCL *1 Input B2 --- I2C_SCL C2 I2C_SDA *1 Input B2 --- I2C_SDA *1: Same as ML7125-001 GPIO pins No Pin Name ML7125-001 Pin Name ML7125-002 Status in reset I/O Active Level Function A3 RF_ACTIVE GPIO0 Low output B2 --- RF_ACTIVE : Status pin indicates RF access activity. GPIO0 : GPIO inout B3 WAKEUP GPIO1 Input B2 --- WAKEUP : Control pin from HOST to wakeup ML7125-001 GPIO1 : GPIO inout/ A4 IRQ GPIO2 High output B2 --- IRQ : Status pin indicates interruption reason taken place in ML7125-001 GPIO2 : GPIO inout B4 PS_CONTRO L GPIO3 Low output B2 --- PS_CONTROL : Status pin indicates deep sleep mode status. GPIO3 : GPIO inout Debugger pins No Pin Name ML7125-001 Pin Name ML7125-002 Status in reset I/O Active Level Function B5 SWD *1 input B2 --- SWD data inout A5 SWCK *1 input I --- SWD clock input *1: Same as ML7125-001 Miscellaneous pins No Pin Name ML7125-001 Pin Name ML7125-002 Status in reset I/O Active Level Function |
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Similar Description - ML7125-001 |
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