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ML620Q134 Datasheet(PDF) 1 Page - LAPIS Semiconductor Co., Ltd. |
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ML620Q134 Datasheet(HTML) 1 Page - LAPIS Semiconductor Co., Ltd. |
1 / 33 page FEDL620Q130-02 Issue Date: May 12, 2016 ML620Q131/2/3/4/5/6 16-bit micro controller 1/33 GENERAL DESCRIPTION This LSI is a high performance CMOS 16-bit microcontroller equipped with an 16-bit CPU nX-U16/100 and integrated with rich peripheral functions such as the timer, PWM, comparator, voltage level supervisor, UART, I2C, and successive approximation type A/D converter. The CPU nX-U16/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipeline architecture parallel processing. It has the data flash memory area which can be written by software. In addition, the on-chip debug function that is installed enables software debugging and programming. FEATURES · CPU - 16-bit RISC CPU (CPU name: nX-U16/100) - Instruction system: 16-bit length instruction ‒ Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on ‒ On-chip debug function built in ‒ Minimum instruction execution time 30.5 μs (at 32.768 KHz system clock) 0.063 μs (at 16 MHz system clock) · Internal memory ‒ Flash memory (program area) Rewrite count 100 cycles ML620Q131: 8 Kbyte (4K x 16 bits) ML620Q132: 16 Kbyte (8K x 16 bits) ML620Q133: 24 Kbyte (12K x 16 bits) ML620Q134: 8 Kbyte (4K x 16 bits) ML620Q135: 16 Kbyte (8K x 16 bits) ML620Q136: 24 Kbyte (12K x 16 bits) ‒ Flash memory (data area) Rewrite count 10,000 cycles 2 Kbyte (1K x 16 bits) ‒ SRAM 2 Kbyte (2K x 8 bits) · Interrupt controller - Non-maskable interrupt source: 2 (Internal sources: BACK-UP CLOCK, WDT) - Maskable interrupt sources: 30 (Internal sources: 25, External sources: 5) - Four interrupt levels and masking function · Time base counter - Low-speed time base counter ´ 1 channel · Watchdog timer ‒ Non-maskable interrupt and reset (The first overflow generates an interrupt, and the second overflow generates a reset) ‒ Free running ‒ Overflow period: 4 types selectable (125 ms, 500 ms, 2 s, and 8 s at 32.768 kHz) |
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