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ML610Q418 Datasheet(PDF) 6 Page - LAPIS Semiconductor Co., Ltd. |
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ML610Q418 Datasheet(HTML) 6 Page - LAPIS Semiconductor Co., Ltd. |
6 / 38 page FEDL610Q418-01 ML610Q418/ML610Q418C 6/38 ML610Q418C Block Diagram Figure 2 show the block diagram of the ML610Q418C. "*" indicates the secondary function of each port. Figure 2 ML610Q418C Block Diagram Program Memory (Flash) 128Kbyte + Data Flash 4Kbyte SSIO ×2 SCK0* SIN0* SOUT0* UART ×2 RXD0* TXD0* I 2C SDA* SCL* INT 2 RAM 4096byte Interrupt Controller CPU (nX-U8/100) Timing Controller EA SP On-Chip ICE Instruction Decoder BUS Controller Instruction Register TBC INT 4 INT 2 INT 1 INT 1 WDT INT 4 8bit Timer ×4 INT 1 PWM GPIO P10 to P11 P20 to P22 INT 5 P30 to P35 P40 to P47 Data-bus PWM0* Melody INT 1 MD0* TEST0 RESET_N OSC XT0 XT1 OSC0* OSC1* LSCLK* OUTCLK* BLD Power VDDL LCD Driver COM0 to COM3 SEG0 to SEG39 LCD BIAS VL1, VL2, VL3 C1, C2 RC-ADC ×2 CS0* IN0* RS0* RT0* CRT0* RCM* CS1* IN1* RS1* RT1* RESET & TEST ALU EPSW1~3 PSW ELR1~3 LR ECSR1~3 DSR/CSR PC GREG 0~15 VDD VSS INT 1 Display register 384bit Display Allocation RAM P00 to P03 TEST1_N P50 to P53 AVDD AVSS 12 bit-ADC AIN0, AIN1, AIN2, AIN3 VREF INT 1 SCK1* SIN1* SOUT1* Capture ×2 P60 to P67 RXD1* TXD1* |
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