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ADG3248BKS-REEL7 Datasheet(PDF) 8 Page - Analog Devices |
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ADG3248BKS-REEL7 Datasheet(HTML) 8 Page - Analog Devices |
8 / 12 page REV. 0 –8– ADG3248 Multiplexing Many systems, such as docking stations and memory banks, have a large number of common bus signals. Common prob- lems faced by designers of these systems include • Large delays caused by capacitive loading of the bus • Noise due to simultaneous switching of the address and data bus signals Figure 6 shows an array of memory banks in which each address and data signal is loaded by the sum of the individual loads. If a bus switch is used as shown in Figure 7, the output load on the memory address and data bits is halved. The speed at which the selected bank’s data can flow is much improved because the capacitance loading is halved and the switches introduce negligible propagation delay. Bus noise is also reduced. MEMORY ADDRESS DATA MEMORY BANK B MEMORY BANK C MEMORY BANK D MEMORY BANK A Figure 6. All Memory Banks Are Permanently Connected to the Bus MEMORY ADDRESS DATA MEMORY BANK B MEMORY BANK C MEMORY BANK D MEMORY BANK A Figure 7. ADG3248 Used to Reduce Both Access Time and Noise |
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