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BR93H46-2C Datasheet(PDF) 4 Page - Rohm |
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BR93H46-2C Datasheet(HTML) 4 Page - Rohm |
4 / 33 page Datasheet Datasheet 4/29 www.rohm.com 16.Feb.2016 Rev.003 TSZ22111・15・001 © 2012 ROHM Co., Ltd. All rights reserved. TSZ02201-0R1R0G100010-1-2 BR93H46-2C Serial Input / Output Timing ○ Data is taken from DI, in sync with the rise of SK. ○ At READ command, data is outputted from DO in sync with the rise of SK. ○ After WRITE command input, the status signal of WRITE (READY / BUSY) can be monitored from DO by setting CS to “H” after tCS, from the fall of CS, and will display a valid status until the next command start bit is inputted. But, if CS is set to “L”, DO sets to High-Z state. ○ To execute a series of commands, CS is set to “L” once after completion of each command for internal circuit reset. Block Diagram Figure 1. Serial Input / Output Timing Diagram tCSS CS SK tDF tSKH tSKL tCSH STATUS VALID DI DO(READ) DO(WRITE) tDIH tDIS tPD0 tPD1 Command decode Control Clock generation Power source voltage detection Write prohibition High voltage occurrence Command register Address buffer SK DI Dummy bit DO Data register R/W amplifier 16bit 16bit 1,024 bit EEPROM CS Address decoder 6bit 6bit Figure 3. Block Diagram |
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