TFP401, TFP401A

TI PanelBus

 DIGITAL RECEIVER

SLDS120B - MARCH 2000 – REVISED JUNE 2003

5

POST OFFICE BOX 655303

Terminal Functions (continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

RxC+

93

AI

Clock positive receiver input – Positive side of reference clock. TMDS low voltage signal differential input pair

RxC–

94

AI

Clock negative receiver input – Negative side of reference clock. TMDS low voltage signal differential input

pair.

Rx0+

90

AI

Channel-0 positive receiver input – Positive side of channel-0. TMDS low voltage signal differential input pair.

Channel-0 receives blue pixel data in active display and HSYNC, VSYNC control signals in blank.

Rx0–

91

AI

Channel-0 negative receiver input – Negative side of channel-0. TMDS low voltage signal differential input

pair.

Rx1+

85

AI

Channel-1 positive receiver input – Positive side of channel-1 TMDS low voltage signal differential input pair.

Channel-1 receives green pixel data in active display and CTL1 control signals in blank.

Rx1–

86

AI

Channel-1 negative receiver input – Negative side of channel-1 TMDS low voltage signal differential input pair

Rx2+

80

AI

Channel-2 positive receiver input – Positive side of channel-2 TMDS low voltage signal differential input pair.

Channel-2 receives red pixel data in active display and CTL2, CTL3 control signals in blank.

Rx2–

81

AI

Channel-2 negative receiver input – Negative side of channel-2 TMDS low voltage signal differential input pair.

SCDT

8

DO

Sync detect – Output to signal when the link is active or inactive. The link is considered to be active when DE is

actively switching. The TFP401/401A monitors the state DE to determine link activity. SCDT can be tied

externally to PDO to power down the output drivers when the link is inactive.

High: Active link

Low: Inactive link

ST

3

DI

Output drive strength select – Selects output drive strength for high or low current drive. (See dc specifications

for IOH and IOL vs ST state.)

High : High drive strength

Low : Low drive strength

STAG

7

DI

Staggered pixel select – An active low signal used in the 2-pixel/clock pixel mode (PIXS = high). Time staggers

the even and odd pixel outputs to reduce ground bounce. Normal operation outputs the odd and even pixels

simultaneously.

High : Normal simultaneous even/odd pixel output

Low: Time staggered even/odd pixel output

VSYNC

47

DO

Vertical sync output

-0.3 V to 4 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, logic/analog signals

-0.3 V to 4 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating ambient temperature range

0

°C to 70°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range

- 65

°C to 150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Case temperature for 10 seconds

260

°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

260

°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package power dissipation/PowerPAD

: Soldered (see Note 1)

4.3 W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Not soldered (see Note 2)

2.7 W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ESD Protection, all pins

2.5 KV Human Body Model

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JEDEC latchup (EIA/JESD78)

100 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. Specified with PowerPAD

 bond pad on the backside of the package soldered to a 2 oz. Cu plate PCB thermal plane. Specified

at maximum allowed operating temperature, 70

°C.

2. PowerPAD

 bond pad on the backside of the package is not soldered to a thermal plane. Specified at maximum allowed operating

temperature, 70

°C.