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ICE3B2065J Datasheet(PDF) 7 Page - Infineon Technologies AG |
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ICE3B2065J Datasheet(HTML) 7 Page - Infineon Technologies AG |
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7 / 28 page  Version 2.9 7 25 Mar 2013 CoolSET®-F3 ICE3Bxx65J 3 Functional Description All values which are used in the functional description are typical values. For calculating the worst cases the min/max values which can be found in section 4 Electrical Characteristics have to be considered. 3.1 Introduction CoolSET ®-F3 Jitter version is the further development of the CoolSET ®-F2 to meet the requirements for the lowest Standby Power at minimum load and no load conditions. A new fully integrated Standby Power concept is implemented into the IC in order to keep the application design easy. Compared to CoolSET ®-F2 no further external parts are needed to achieve the lowest Standby Power. An intelligent Active Burst Mode is used for this Standby Mode. After entering this mode there is still a full control of the power conversion by the secondary side via the same optocoupler that is used for the normal PWM control. The response on load jumps is optimized. The voltage ripple on V out is minimized. V out is further on well controlled in this mode. The usually external connected RC-filter in the feedback line after the optocoupler is integrated in the IC to reduce the external part count. Furthermore a high voltage Startup Cell is integrated into the IC which is switched off once the Undervoltage Lockout on-threshold of 18V is exceeded. This Startup Cell is part of the integrated CoolMOS ®. The external startup resistor is no longer necessary as this Startup Cell is connected to the Drain. Power losses are therefore reduced. This increases the efficiency under light load conditions drastically. The Soft-Start capacitor is also used for providing an adjustable blanking window for high load jumps. During this time window the overload detection is disabled. With this concept no further external components are necessary to adjust the blanking window. An Auto Restart Mode is implemented in the IC to reduce the average power conversion in the event of malfunction or unsafe operating condition in the SMPS system. This feature increases the system’s robustness and safety which would otherwise lead to a destruction of the SMPS. Once the malfunction is removed, normal operation is automatically initiated after the next Start Up Phase. The internal precise peak current limitation reduces the costs for the transformer and the secondary diode. The influence of the change in the input voltage on the power limitation can be avoided together with the integrated Propagation Delay Compensation. Therefore the maximum power is nearly independent on the input voltage which is required for wide range SMPS. There is no need for an extra over-sizing of the SMPS, e.g. the transformer or the secondary diode. 3.2 Power Management Figure 3 Power Management The Undervoltage Lockout monitors the external supply voltage V VCC. When the SMPS is plugged to the main line the internal Startup Cell is biased and starts to charge the external capacitor C VCC which is connected to the VCC pin. The VCC charge current that is provided by the Startup Cell from the Drain pin is 1.05mA. When V VCC exceeds the on-threshold V CCon=18V, bias circuit is switched on. Then the Startup Cell is switched off by the Undervoltage Lockout and therefore no power losses present due to the connection of the Startup Cell to the Drain voltage. To avoid uncontrolled ringing at switch-on a hysteresis is implemented. The switch-off of the controller can only take place after active mode was entered and V VCC falls below 10.3V. The maximum current consumption before the controller is activated is about 300uA. Internal Bias Voltage Reference Power Management 5V VCC Undervoltage Lockout 18V 10.3 T1 Power-Down Reset SoftS Active Burst Mode Auto Restart Mode Startup Cell Drain |
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