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IS45SM32100D-75BLA1 Datasheet(PDF) 3 Page - Integrated Silicon Solution, Inc

Part # IS45SM32100D-75BLA1
Description  512K x 32Bits x 2Banks Low Power Synchronous DRAM
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Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS45SM32100D-75BLA1 Datasheet(HTML) 3 Page - Integrated Silicon Solution, Inc

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IS42/45SM/RM/VM32100D
www.issi.com - dram@issi.com
Rev. A | November 2015
Table2: Pin Descriptions
Pin
Pin Name
Descriptions
CLK
System Clock
The system clock input. All other inputs are registered to the
SDRAM on the rising edge CLK.
CKE
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM
will be one of the states among power down, suspend or self
refresh.
/CS
Chip Select
Enable or disable all inputs except CLK, CKE and DQM.
BA
Bank Address
Selects bank to be activated during RAS activity.
Selects bank to be read/written during CAS activity.
A0~A10
Address
Row Address
: RA0~RA10
Column Address
: CA0~CA7
Auto Precharge
: A10
/RAS, /CAS, /WE
Row Address Strobe,
Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation.
Refer function truth table for details.
DQM0~DQM3
Data Input/Output Mask
Controls output buffers in read mode and masks input data in
write mode.
DQ0~DQ31
Data Input/Output
Data input/output pin.
VDD/VSS
Power Supply/Ground
Power supply for internal circuits and input buffers.
VDDQ/VSSQ
Data Output Power/Ground
Power supply for output buffers.
NC
No Connection
No connection.


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