Integrated Silicon Solution, Inc. - www.issi.com

7

Rev. B

2/5/2015

IS42VS83200J / IS42VS16160J / IS42VS32800J

Burst Length

Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in

MODE REGISTER DEFINITION. The burst length determines the maximum number of column locations that can

be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4 or 8 locations are available for both the

sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst

is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states

should not be used, as unknown operation or incompatibility with future versions may result.

When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All

accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is

reached. The block is uniquely selected by A1-A8 (x32), A1-A8 (x16) or A1-A9 (x8) when the burst length is set to two;

by A2-A8 (x32), A2-A8 (x16) or A2-A9 (x8) when the burst length is set to four; and by A3-A8 (x32), A3-A8 (x16) or

A3-A9 (x8) when the burst length is set to eight. The remaining (least significant) address bit(s) are used to select the

starting location within the block. Full-page bursts wrap within the page if the boundary is reached.

MODE REGISTER DEFINITION

Latency Mode

M6 M5 M4

CAS Latency

0

0

0

Reserved

0

0

1

Reserved

0

1

0

2

0

1

1

3

1

0

0

Reserved

1

0

1

Reserved

1

1

0

Reserved

1

1

1

Reserved

1. Note: A12 x8 and x16, A11 x32

2. To ensure compatibility with future devices,

should program A12, A11, A10 = "0"

Write Burst Mode

M9

Mode

0

Programmed Burst Length

1

Single Location Access

Operating Mode

M8 M7

M6-M0

Mode

0

0

Defined

Standard Operation

— —

—

All Other States Reserved

Burst Type

M3

Type

0

Sequential

1

Interleaved

Burst Length

M2 M1 M0

M3=0

M3=1

0

0

0

1

1

0

0

1

2

2

0

1

0

4

4

0

1

1

8

8

1

0

0

Reserved

Reserved

1

0

1

Reserved

Reserved

1

1

0

Reserved

Reserved

1

1

1

Full Page

Reserved

Reserved

Address Bus (Ax)

Mode Register (Mx)

(1)

BA1 BA0 A12 A11 A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

BA1

BA0

Mode Register Definition

0

0

Program Mode Register

0

1

Reserved

1

0

Program Extended Mode Register

1

1

Reserved