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S5D0127X01-Q0R0 Datasheet(PDF) 11 Page - Samsung semiconductor |
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S5D0127X01-Q0R0 Datasheet(HTML) 11 Page - Samsung semiconductor |
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11 / 96 page  ELECTRONICS S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 11 OF 96 Modified on May/04/2000 When in digital input mode, all programmable timing registers (such as HAVB,HAVE, HS2B etc.) are still functional. If HS1 and VS are programmed as inputs, the associated output timing controls such as HS1B,E will have no effect. An example of horizontal timing for digital input is shown in Figure 4. Figure 4. Horizontal Timing for EXV Port as Digital Input 1.1.5. Additional Information for Analog Component Video Input For the S5D0127X01 to correctly set the V component phase in analog component video input mode, PID (pin 17) and PORTA (pin 58) need to be connected together. PORTA has to be configured as input (DIRA = 0) and connected to the internal CBG signal (DATAA[2:0] = 3). It is also recommended that external clamp circuit be used for Cb and Cr inputs (before the coupling caps) and the internal chroma clamp be disabled (COFFENB = 1) due to slight Cb/Cr leakage. 80 10 80 10 80 10 U0 Y0 V0 Y1 U2 Y2 V2 Y3 U4 Y4 V4 Y5 U6 Y6 V6 Y7 Ux Yx Vx Yx Ux HAV CK CK2 HS1 80 10 80 10 80 10 U0 Y0 V0 Y1 U2 Y2 V2 Y3 U4 Y4 V4 Y5 U6 Y6 V6 Y7 Ux Yx Vx Yx Ux Yx Vx Yx Vx Programmable, when an Fully programmable HAVB location HAV -- fully programmable, Defines location of first, last pixel and defines Cb,Y,Cr data location Data group delay through chip -- EXV[7:0] output - Any input phase is acceptable Constant to internal counter reference based on internal counter Fully programmable HAVE location The CK2 output clock phasing is aligned to the HAV leading edge CK can be input or output This HS1 location can also come From a 656 SAV code Y[7:0] Y output for OFMT=2 is shown, any 8 or 16 bit output format is allowed. |
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