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TMS320F28334ZJZQ Datasheet(PDF) 4 Page - Texas Instruments |
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TMS320F28334ZJZQ Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 201 page  L0 SARAM 4K x 16 (0-Wait, Dual Map) L1 SARAM 4K x 16 (0-Wait, Dual Map) L2 SARAM 4K x 16 (0-Wait, Dual Map) L3 SARAM 4K x 16 (0-Wait, Dual Map) M0 SARAM 1Kx16 (0-Wait) M1 SARAM 1Kx16 (0-Wait) L4 SARAM 4K x 16 (0-W Data, 1-W Prog) L5 SARAM 4K x 16 (0-W Data, 1-W Prog) L6 SARAM 4K x 16 (0-W Data, 1-W Prog) L7 SARAM 4K x 16 (0-W Data, 1-W Prog) Boot ROM 8K x 16 Code Security Module PSWD OTP 1K x 16 Flash 256K x 16 8 Sectors Pump Flash Wrapper TEST1 TEST2 XA0/XWE1 XWE0 XZCS6 XZCS7 XZCS0 XR/W XREADY XHOLD XHOLDA XD31:0 XA19:1 GPIO MUX Memory Bus XCLKOUT XRD GPIO MUX 88 GPIOs 8 External Interrupts 88 GPIOs 12-Bit ADC 2-S/H A7:0 B7:0 CPU Timer 0 CPU Timer 1 CPU Timer 2 OSC, PLL, LPM, WD DMA 6 Ch PIE (Interrupts) 32-bit CPU (150 MHZ @ 1.9 V) (100 MHz @ 1.8 V) EMU1 EMU0 TRST TDO TMS TDI TCK XRS X2 X1 XCLKIN FPU REFIN DMA Bus Memory Bus FIFO (16 Levels) SCI-A/B/C FIFO (16 Levels) SPI-A FIFO (16 Levels) I2C 16-bit peripheral bus McBSP-A/B 32-bit peripheral bus (DMA accessible) ePWM-1/../6 HRPWM-1/../6 eCAP-1/../6 eQEP-1/2 CAN-A/B (32-mbox) 32-bit peripheral bus GPIO MUX 88 GPIOs XINTF Secure zone Copyright © 2016, Texas Instruments Incorporated 4 TMS320F28335, TMS320F28334, TMS320F28333, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439N – JUNE 2007 – REVISED OCTOBER 2016 www.ti.com Submit Documentation Feedback Product Folder Links: TMS320F28335 TMS320F28334 TMS320F28333 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232 Device Overview Copyright © 2007–2016, Texas Instruments Incorporated 1.4 Functional Block Diagram Figure 1-1. Functional Block Diagram |
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