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PHILIPS |
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Philips Semiconductors Preliminary data PDI1394P25 1-port 400 Mbps physical layer interface 2001 Sep 06 3 4.0 PIN AND BALL CONFIGURATION 4.1 LQFP CONFIGURATION SV01828 1 2 3 4 5 6 7 19 20 21 22 23 24 25 LREQ SYSCLK CNA CTL0 CTL1 D1 D0 26 27 17 18 8 9 10 11 D2 D3 D5 D4 12 13 14 15 D7 PD LPS NC 28 29 30 31 32 48 47 46 45 44 43 42 AGND NC NC NC NC AVDD NC 41 40 39 38 R1 R0 TPBIAS0 AGND 37 36 35 34 TPA0+ TPA0– TPB0+ TPB0– 62 61 60 59 58 57 56 55 54 64 63 53 52 51 50 49 16 D6 33 AGND PDI1394P25 |