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Rev. A | November 2015

IS42/45SM/RM/VM16800H

Table4: Command Truth Table

Function

CKEn-1

CKEn

/CS

/RAS

/CAS

/WE

DQM

ADDR

A10

Note

Device Deselect (NOP)

H

X

H

X

X

X

X

X

No Operation (NOP)

H

X

L

H

H

H

X

X

Mode Register Set

H

X

L

L

L

L

X

OP CODE

4

Extended Mode Register Set

H

X

L

L

L

L

X

OP CODE

4

Active (select bank and

activate row)

H

X

L

L

H

H

X

Bank/Row

Read

H

X

L

H

L

H

L/H

Bank/Col

L

5

Read with Autoprecharge

H

X

L

H

L

H

L/H

Bank/Col

H

5

Write

H

X

L

H

L

L

L/H

Bank/Col

L

5

Write with Autoprecharge

H

X

L

H

L

L

L/H

Bank/Col

H

5

Precharge All Banks

H

X

L

L

H

L

X

X

H

Precharge Selected Bank

H

X

L

L

H

L

X

Bank

L

Burst Stop

H

H

L

H

H

L

X

X

Auto Refresh

H

H

L

L

L

H

X

X

3

Self Refresh Entry

H

L

L

L

L

H

X

X

3

Self Refresh Exit

L

H

H

X

X

X

X

X

2

L

H

H

H

Precharge Power Down Entry

H

L

H

X

X

X

X

X

L

H

H

H

Precharge Down Exit

L

H

H

X

X

X

X

X

L

H

H

H

Clock Suspend Entry

H

L

H

X

X

X

X

X

L

V

V

V

Clock Suspend Exit

L

H

X

X

X

Deep Power Down Entry

H

L

L

H

H

L

X

X

6

Deep Power Down Exit

L

H

X

X

X

Note :

1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.

H: High Level, L: Low Level, X: Don't Care, V: Valid

2. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high and will put the device in the all banks idle state once

tXSR is met. Command Inhibit or NOP commands should be issued on any clock edges occuring during the tXSR period. A minimum

of two NOP commands must be provided during tXSR period.

3. During refresh operation, internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.

4. A0-A11 define OP CODE written to the mode register, and BA must be issued 0 in the mode register set, and 1 in the extended

mode register set.

5. DQM “L” means the data Write/Ouput Enable and “H” means the Write inhibit/Output High-Z. Write DQM Latency is 0 CLK and Read

DQM Latency is 2 CLK.

6. Standard SDRAM parts assign this command sequence as Burst Terminate. For Bat Ram parts, the Burst Terminate command is

assigned to the Deep Power Down function.