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TSB83AA22CZAJ Datasheet(PDF) 9 Page - Texas Instruments |
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TSB83AA22CZAJ Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 115 page  www.ti.com 1 Introduction 1.1 Features TSB83AA22C IEEE Std 1394b-2002 PHY and OHCI Link Device SLLS802 – FEBRUARY 2007 Ensure That TSB83AA22C Does Not Load • Fully Supports Provisions of IEEE Std TPBIAS of Any Connected Device and Blocks 1394b-2002 Revision 1.33+ at 1-Gigabit Signaling Rates Any Leakage From the Port Back to Power Plane • Fully Supports Provisions of IEEE Std 1394a-2000 and IEEE Std 1394-1995 for • IEEE Std 1394a-2000-Compliant High-Performance Serial Bus Common-Mode Noise Filter on Incoming Bias Detect Circuit to Filter Out Crosstalk Noise • Fully Interoperable With Firewire™, i.LINK™, and SB1394 Implementations of IEEE Std 1394 • Port Programmable to Force IEEE Std 1394a-2000 Mode to Allow Use of IEEE Std • Provides Two Fully Backward-Compatible, 1394a-2000 Connectors (IEEE Std 1394b-2002 (IEEE Std 1394a-2000 Fully Compliant) Signaling Must Not Be Put Across IEEE Std Bilingual IEEE Std 1394b-2002 Cable Ports at 1394a-2000 Connectors or Cables) up to 800 Megabits per Second (Mbps) • 3.3-V and 5-V PCI Signaling Environments • Full IEEE Std 1394a-2000 Support Includes: • Serial-Bus Data Rates of 100 Mbps, 200 Mbps, – Connection Debounce 400 Mbps, and 800 Mbps – Arbitrated Short Reset – Multispeed Concatenation • Physical Write Posting of up to Three Outstanding Transactions – Arbitration Acceleration – Fly-By Concatenation • Serial ROM or Boot ROM Interface Supports – Port Disable/Suspend/Resume 2-Wire Serial EEPROM Devices • Extended Resume Signaling for Compatibility • 33-MHz/32-Bit PCI Interface With Legacy DV Devices • Multifunction Terminal (MFUNC Terminal 1): • Power-Down Features to Conserve Energy in – PCI_CLKRUN Protocol Per PCI Mobile Battery-Powered Applications Design Guide – General-Purpose I/O (GPIO) • Low-Power Sleep Mode – CYCLEIN/CYCLEOUT for External Cycle • Fully Compliant With Open Host Controller Timer Control for Customized Interface (OHCI) Requirements Synchronization • Cable Power Presence Monitoring • PCI Burst Transfers and Deep FIFOs to • Cable Ports Monitor Line Conditions for Active Tolerate Large Host Latency Connection to Remote Node – Transmit FIFO—5K Asynchronous • Register Bits Give Software Control of – Transmit FIFO—2K Isochronous Contender Bit, Power-Class Bits, Link Active – Receive FIFO—2K Asynchronous Control Bit, and IEEE Std 1394a-2000 Features – Receive FIFO—2K Isochronous • Interoperable With Other 1394 Physical Layers • D0, D1, D2, and D3 Power States and PME (PHYs) Using 1.8-V, 3.3-V, and 5-V Supplies Events Per PCI Bus Power Management • Low-Jitter, External Crystal Oscillator Provides Interface Specification Transmit and Receive Data at 100/200/400/800 • Programmable Asynchronous Transmit Mbps and Link-Layer Controller Clock at Threshold 49.152 MHz and 98.304 MHz • Isochronous Receive Dual-Buffer Mode • Separate Bias (TPBIAS) for Each Port • Out-of-Order Pipelining for Asynchronous • Software Device Reset (SWR) Transmit Requests • Fail-Safe Circuitry Senses Sudden Loss of • Initial-Bandwidth-Available and Power to the Device and Disables Ports to Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. OHCI-Lynx is a trademark of Texas Instruments. Firewire is a trademark of Apple Computer, Inc. i.LINK is a trademark of Sony Kabushiki Kaisha TA Sony Corporation. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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