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NOIP3FN1300A-QTI Datasheet(PDF) 5 Page - ON Semiconductor |
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NOIP3FN1300A-QTI Datasheet(HTML) 5 Page - ON Semiconductor |
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5 / 75 page  NOIP1SN1300A www.onsemi.com 5 Table 5. ELECTRICAL SPECIFICATIONS Boldface limits apply for TJ = TMIN to TMAX, all other limits TJ = +30°C. (Notes 5, 6, 7, 8 and 9) Parameter Unit Max Typ Min Description fserclock Clock rate of output clock Clock output for mesochronous signaling 360 MHz Vicm LVDS input common mode level 0.3 1.25 1.8 V Tccsk Channel to channel skew (Training pattern allows per channel skew correction) 50 ps I/O − P2−SN/SE CMOS (JEDEC− JESD8C−01): Conforming to standard/additional specifications and deviations listed fpardata Data rate on parallel channels (10−bit) 72 Mbps Cout Output load (only capacitive load) 10 pF tr Rise time (10% to 90% of input signal) 2.5 4.5 6.5 ns tf Fall time (10% to 90% of input signal) 2 3.5 5 ns Electrical Interface − P1 − SN/SE/FN LVDS fin Input clock rate when PLL used 72 MHz fin Input clock when LVDS input used 360 MHz tidc Input clock duty cycle when PLL used 45 50 55 % tj Input clock jitter 20 ps ratspi (= fin/fspi) 10−bit (4 LVDS channels), PLL used (fin = 72 MHz) 6 10−bit (2 LVDS channels), PLL used (fin = 72 MHz) 12 10−bit (1 LVDS channel), PLL used (fin = 72 MHz) 24 10−bit (4 LVDS channels), LVDS input used (fin = 360 MHz) 30 10−bit (2 LVDS channels), LVDS input used (fin = 360 MHz) 60 10−bit (1 LVDS channel), LVDS input used (fin = 360 MHz) 120 8−bit (4 LVDS channels), PLL used (fin = 72 MHz) 6 8−bit (2 LVDS channels), PLL used (fin = 72 MHz) 12 8−bit (1 LVDS channel), PLL used (fin = 72 MHz) 24 8−bit (4 LVDS channels), LVDS input used (fin = 288 MHz) 24 8−bit (2 LVDS channels), LVDS input used (fin = 288 MHz) 48 8−bit (1 LVDS channel), LVDS input used (fin = 288 MHz) 96 Electrical Interface − P2−SN/SE CMOS fin Input clock rate 72 MHz tidc Input clock duty cycle 45 50 55 % tj Input clock jitter 20 ps ratspi (= fin/fspi) 10−bit, PLL bypassed (fin = 72 MHz) 24 Electrical Interface − P3 − SN/SE/FN LVDS fin Input clock rate when PLL used 72 MHz fin Input clock when LVDS input used 360 MHz tidc Input clock duty cycle when PLL used 45 50 55 % tj Input clock jitter 20 ps Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. All parameters are characterized for DC conditions after thermal equilibrium is established. 6. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is recommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high impedance circuit. 7. Minimum and maximum limits are guaranteed through test and design. 8. Refer to ACSPYTHON1300 available at the Image Sensor Portal for detailed acceptance criteria specifications. 9. For power supply management recommendations, please refer to Application Note AND9158. |
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