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NCV7428MW5R2G Datasheet(PDF) 4 Page - ON Semiconductor

Part # NCV7428MW5R2G
Description  System Basis Chip with Integrated LIN and Voltage Regulator
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NCV7428MW5R2G Datasheet(HTML) 4 Page - ON Semiconductor

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Table 3. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
Max
Units
VS
Maximum DC voltage at VS pin
−0.3
45
V
VOUT
Maximum voltage at VOUT pin
−0.3
6
V
VLIN
Maximum voltage at LIN bus pin
−45
45
V
VDig_IO_inputs
Maximum voltage at digital input pins (TxD, EN)
−0.3
45
V
VDig_IO_outputs
Maximum voltage at digital output pins (RxD, RSTN)
−0.3
VOUT+0.3
V
TAMB
Ambient temperature range
−40
+125
°C
TJ
Junction temperature range
−40
+170
°C
TSTG
Storage temperature range
−55
+150
°C
VESD
System ESD at pins VS, LIN as per IEC 61000−4−2: 330
W / 150 pF
(Verified by external test house)
≥ ±14
kV
Human body model at pins VS, LIN stressed towards GND with 1500
W / 100 pF
≥ ±8
kV
Human body model at all pins as per JESD22−A114 / AEC−Q100−002
≥ ±4
kV
Charge device model at all pins as per JESD22−C101 / AEC−Q100−011
≥ ±500
V
Machine model; (200 pF; 0.75
mH; 10 W) as per JESD22−A115 / AEC−Q100−003
±200
V
MSL
Moisture Sensitivity Level
SOIC
DFN
2
1
TSLD
Lead temperature Soldering − Reflow (SMD styles only), Pb−Free (Note 1)
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Table 4. OPERATING RANGES
Symbol
Parameter
Min
Max
Units
VS
VS operating voltage for parametric operation (Note 2)
5.5
28
V
VS operating voltage for limited operation (Note 2)
4
28
V
VOUT5
Regulated voltage at VOUT supply output for 5 V versions
4.9
5.1
V
VOUT33
Regulated voltage at VOUT supply output for 3.3 V versions
3.234
3.366
V
IVOUT
Current delivered by the VOUT regulator
70
mA
VLIN
Operating voltage at LIN bus pin
0
VS
V
VDig_IO_inputs
Operating voltage at digital input pins (TxD, EN)
0
5.5
V
VDig_IO_outputs
Operating voltage at digital output pins (RxD, RSTN)
0
VOUT
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
2. Below 5.5 V at VS pin in normal mode, the bus will either stay recessive or comply with the voltage level specifications and transition time
specifications as required by SAE J2602. It is ensured by the battery monitoring circuit. Above 28 V at VS pin, LIN communication is
operational (LIN pin toggling) but parameters cannot be guaranteed. For higher battery voltage operation above 28 V, LIN pull−up resistor
must be selected large enough to avoid clamping of LIN pin by voltage drop over external pull−up resistor and LIN pin min current limitation.
Table 5. THERMAL CHARACTERISTICS
Rating
Symbol
Value
Unit
Thermal Characteristics, SOIC−8 (Note 3)
Thermal Resistance Junction−to−Air, Free air, 1S0P PCB (Note 4)
Thermal Resistance Junction−to−Air, Free air, 2S2P PCB (Note 5)
RqJA
RqJA
125
75
°C/W
°C/W
Thermal Characteristics, DFN−8 (Note 3)
Thermal Resistance Junction−to−Air, Free air, 1S0P PCB (Note 4)
Thermal Resistance Junction−to−Air, Free air, 2S2P PCB (Note 5)
RqJA
RqJA
133
55
°C/W
°C/W
3. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
4. Values based on test board according to EIA/JEDEC Standard JESD51−3, signal layer with 10% trace coverage.
5. Values based on test board according to EIA/JEDEC Standard JESD51−7, signal layers with 10% trace coverage for the signal layer and
4 thermal vias connected between exposed pad and first inner Cu layer.


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