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M28W320ECT85N6T Datasheet(PDF) 5 Page - STMicroelectronics |
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M28W320ECT85N6T Datasheet(HTML) 5 Page - STMicroelectronics |
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5 / 53 page  5/53 M28W320ECT, M28W320ECB SUMMARY DESCRIPTION The M28W320EC is a 32 Mbit (2 Mbit x 16) non- volatile Flash memory that can be erased electri- cally at the block level and programmed in-system on a Word-by-Word basis. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. VDDQ allows to drive the I/O pin down to 1.65V. An optional 12V VPP power supply is provided to speed up customer programming. The device features an asymmetrical blocked ar- chitecture. The M28W320EC has an array of 71 blocks: 8 Parameter Blocks of 4 KWord and 63 Main Blocks of 32 KWord. M28W320ECT has the Parameter Blocks at the top of the memory ad- dress space while the M28W320ECB locates the Parameter Blocks starting from the bottom. The memory maps are shown in Figure 5, Block Ad- dresses. The M28W320EC features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling in- stant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any acciden- tal programming or erasure. There is an additional hardware protection against program and erase. When VPP ≤ VPPLK all blocks are protected against program or erase. All blocks are locked at Power Up. Each block can be erased separately. Erase can be suspended in order to perform either read or program in any other block and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles. The device includes a Protection Register to in- crease the protection of a system design. The Pro- tection Register is divided into two segments, the first is a 64 bit area which contains a unique device number written by ST, while the second is a 128 bit area, one-time-programmable by the user. The user programmable segment can be permanently protected. Figure 6, shows the Protection Register Memory Map. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller takes care of the tim- ings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The memory is offered in TSOP48 (10 X 20mm) and TFBGA47 (6.39 x 6.37mm, 0.75mm pitch) packages and is supplied with all the bits erased (set to ’1’). Figure 2. Logic Diagram Table 1. Signal Names A0-A20 Address Inputs DQ0-DQ15 Data Input/Output E Chip Enable G Output Enable W Write Enable RP Reset WP Write Protect VDD Core Power Supply VDDQ Power Supply for Input/Output VPP Optional Supply Voltage for Fast Program & Erase VSS Ground NC Not Connected Internally AI05517 21 A0-A20 W DQ0-DQ15 VDD M28W320ECT M28W320ECB E VSS 16 G RP WP VDDQ VPP |
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