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LM1253A Datasheet(PDF) 7 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # LM1253A
Description  Monolithic Triple 180 MHz I2C CRT Pre-amp With Integrated Analog On Screen Display (OSD) Generator
Download  57 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

LM1253A Datasheet(HTML) 7 Page - National Semiconductor (TI)

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External Interface Signals Electrical Characteristics (Continued)
(See
Figure 3 for Test Circuit)
Unless otherwise noted: V
CC = +5V, VIN = 0.7V, CL = 8 pF, Video Signal Output = 1 VPP,TA = 25˚C, VABL =VCC.
Symbol
Parameter
Conditions
LM1253A
Units
Min
Typ
Max
V
CCDET
V
CC Undervoltage Detection Threshold
3.9
V
F
FREE_RUN
Free Run HBLANK Frequency
30
60
kHz
V
IL
Low Level Input Voltage for SDA and SCL
Pins
1.5
V
V
IH
High Level Input Voltage for SDA and SCL
Pins
3V
V
OL
Low Level Output Voltage for SDA and SCL
Pins
3 mA Sink Current
0
0.4
V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ranges indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and
test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may
change when the device is not operated under the listed test conditions.
Note 3: All voltages are measured with respect to GND, unless otherwise specified.
Note 4: Linearity Error = 100*(stepmax–stepmin)/stepave
Where: The input signal is a 16 step staircase signal waveform with 0.7 VP-P level, subdivided into 16 equal steps, with each step approximately 100 ns in width
stepmax is the maximum voltage step at the output
stepmin is the minimum voltage step at the output
stepave is the average voltage of the 16 steps at the output.
Note 5: Input from signal generator: tr,tf < 1 ns.
Note 6: ABL should provide smooth decrease in gain over the operational range of 0 dB to −5 dB
∆AABL = A(VABL =VABL MAX GAIN)–A (VABL =VABL MIN GAIN)
Test Circuit
DS101265-3
Note: 8 pF load includes parasitic capacitance
FIGURE 3. Test Circuit
www.national.com
7


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