33395

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

10

SYSTEM /APPLICATION INFORMATION

INTRODUCTION

The 33395 and 33395T devices are designed to provide the

necessary drive and control signal buffering and amplification to

enable a DSP or MCU to control a three-phase array of power

MOSFETs such as would be required to energize the windings

of powerful brushless DC (BLDC) motors. It contains built-in

charge pump circuitry so that the MOSFET array may consist

entirely of N-Channel MOSFETs. It also contains feedback

sensing circuitry and control circuitry to provide a robust overall

motor control design.

FUNCTIONAL DESCRIPTION

Gate Drive Circuits

The gate drive outputs (GDH1, GDH2, etc.) supply the peak

currents required to turn ON and hold ON the MOSFETs, as

well as turn OFF and hold OFF the MOSFETs.

Charge Pump

The current capability of the charge pump is sufficient to

supply the gate drive circuit’s demands when PWM’ing at up to

28 kHz. Two external charge pump capacitors and a reservoir

capacitor are required to complete the charge pump’s circuitry.

Charge reservoir capacitance is a function of the total

following formula:

Proper charge pump capacitance is required to maintain,

and provide for, adequate gate drive during high demand turn-

ON intervals. Use the following formula to determine values for

determined:

Thermal Shutdown Function

The device has internal temperature sensing circuitry which

activates a protective shutdown function should the die reach

excessively elevated temperatures. This function effectively

limits power dissipation and thus protects the device.

Overvoltage Shutdown Function

voltage shutdown level, the part will automatically shut down to

protect both internal circuits as well as the load. Operation will

Low Voltage Reset Function

minimum voltage level or when the part is initially powered up,

this function will turn OFF and hold OFF the external MOSFETs

until the voltage increases above the minimum voltage level

required for normal operation.

Control Logic

The control logic block controls when the low-side and high-

side drivers are enabled. The logic implements the Truth Table

found in the specification and monitors the M0, M1, PWM, CL,

OT, OV, LSE, and HSE terminals. Note that the drivers are

enabled 3

µs after the PWM edge. During complimentary chop

mode the high-side and low-side drives are alternatively

enabled and disabled during the PWM cycle. To prevent shoot-

page 9).

(60 nC) x (14 V)

= 0.15

µF

20

10

0.15

µF

20

= 0.075

µF, lower limit; and

10

0.15

µF

= .015

µF, upper limit

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com