NCV7351, NCV7351F

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6

Definitions: All voltages are referenced to GND (pin 2). Positive currents flow into the IC. Sinking current means the current

is flowing into the pin; sourcing current means the current is flowing out of the pin.

Table 4. ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Conditions

Min

Max

Unit

−0.3

+6

V

DC voltage at pin CANH

−50

+50

V

DC voltage at pin CANL

−50

+50

V

Notes 4 and 5

−0.3

+6

V

Electrostatic discharge voltage at all pins

according to EIA−JESD22

Note 6

−6

+6

kV

Electrostatic discharge voltage at

CANH,CANL, pins according to

EIA−JESD22

Note 6

−8

+8

kV

Electrostatic discharge voltage at CANH

,

CANL pins According to IEC 61000−4−2

Note 7

−15

+15

kV

Standardized charged device model ESD

pulses according to ESD−STM5.3.1−1999

−750

+750

V

Transient voltage at CANH, CANL pins,

See Figure 4

Note 8

−150

+100

V

Latch−up

Static latch−up at all pins

Note 9

+150

mA

Storage temperature

−55

+150

°C

Maximum junction temperature

−40

+170

°C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

4. EN pin Only available on NCV7351−E version

6. Standardized human body model electrostatic discharge (ESD) pulses in accordance to EIA−JESD22. Equivalent to discharging a 100 pF

capacitor through a 1.5 k

W resistor.

7. System human body model electrostatic discharge (ESD) pulses. Equivalent to discharging a 150 pF capacitor through a 330

W resistor

referenced to GND. Verified by external test house

8. Pulses 1, 2a,3a and 3b according to ISO 7637 part 3. Results were verified by external test house.

9. Static latch−up immunity: Static latch−up protection level when tested according to EIA/JESD78.

Table 5. THERMAL CHARACTERISTICS

Symbol

Parameter

Conditions

Value

Unit

Thermal Resistance Junction−to−Air, 1S0P PCB (Note 10)

Free air

125

K/W

Thermal Resistance Junction−to−Air, 2S2P PCB (Note 11)

Free air

75

K/W

10. Test board according to EIA/JEDEC Standard JESD51−3, signal layer with 10% trace coverage.

11. Test board according to EIA/JEDEC Standard JESD51−7, signal layers with 10% trace coverage.