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TRS3253EMRSMREP Datasheet(PDF) 5 Page - Texas Instruments |
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TRS3253EMRSMREP Datasheet(HTML) 5 Page - Texas Instruments |
5 / 21 page TRS3253E-EP www.ti.com SLLSEF5 – DECEMBER 2013 ABSOLUTE MAXIMUM RATINGS (1) over junction temperature range (unless otherwise noted) MIN MAX UNIT VCC to GND –0.3 6 V VL to GND –0.3 VCC + 0.3 V V+ to GND –0.3 7 V V– to GND 0.3 –7 V V+ + |V–|(2) 13 V DIN, FORCEOFF to GND, FORCEON to GND –0.3 6 VI Input voltage V RIN to GND ±25 DOUT to GND ±13.2 VO Output voltage V ROUT –0.3 VL + 0.3 TJ Junction temperature 150 °C Tstg Storage temperature range –65 150 °C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. (2) V+ and V– can have maximum magnitudes of 7 V, but their absolute difference cannot exceed 13 V. THERMAL INFORMATION TRS3253E-EP THERMAL METRIC(1) RSM UNITS 32 PINS θJA Junction-to-ambient thermal resistance(2) 37.2 θJCtop Junction-to-case (top) thermal resistance(3) 30.1 θJB Junction-to-board thermal resistance(4) 7.8 °C/W ψJT Junction-to-top characterization parameter(5) 0.4 ψJB Junction-to-board characterization parameter(6) 7.6 θJCbot Junction-to-case (bottom) thermal resistance(7) 2.4 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). (6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). (7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TRS3253E-EP |
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