TRS3253E-EP

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SLLSEF5 – DECEMBER 2013

ABSOLUTE MAXIMUM RATINGS

(1)

over junction temperature range (unless otherwise noted)

MIN

MAX

UNIT

–0.3

6

V

–0.3

V

V+ to GND

–0.3

7

V

V– to GND

0.3

–7

V

13

V

DIN, FORCEOFF to GND, FORCEON to GND

–0.3

6

Input voltage

V

RIN to GND

±25

DOUT to GND

±13.2

Output voltage

V

ROUT

–0.3

Junction temperature

150

°C

Storage temperature range

–65

150

°C

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the

specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

(2)

V+ and V– can have maximum magnitudes of 7 V, but their absolute difference cannot exceed 13 V.

THERMAL INFORMATION

TRS3253E-EP

RSM

UNITS

32 PINS

37.2

30.1

7.8

°C/W

0.4

7.6

2.4

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5)

The junction-to-top characterization parameter,

from the simulation data for obtaining

(6)

The junction-to-board characterization parameter,

from the simulation data for obtaining

(7)

The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

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