Shutdown Mode

In shutdown mode, the reference and reference buffer

shut down between conversions. Shutdown mode

reduces supply current to 0.5µA (typ) immediately after

the conversion. The next falling edge of CS with R/C

low causes the reference and buffer to wake up and

enter acquisition mode. To achieve 16-bit accuracy,

internal reference to wake up.

Internal and External Reference

Internal Reference

The internal reference of the MAX1179/MAX1187/

MAX1189 is internally buffered to provide +4.096V out-

put at REF. Bypass REF to AGND and REFADJ to

AGND with 10µF and 0.1µF, respectively.

Sink or source current at REFADJ to make fine adjust-

ments to the internal reference. The input impedance of

REFADJ is nominally 5k

Ω. Use the circuit of Figure 7 to

adjust the internal reference to ±1.5%.

External Reference

An external reference can be placed at either the input

(REFADJ) or the output (REF) of the MAX1179/

MAX1187/MAX1189’s internal buffer amplifier. Using

the buffered REFADJ input makes buffering the external

reference unnecessary. The input impedance of

REFADJ is typically 5k

Ω. The internal buffer output

must be bypassed at REF with a 10µF capacitor.

Directly drive REF using an external 3.8V to 4.2V refer-

ence. During conversion, the external reference must

be able to drive 100µA of DC load current and have an

output impedance of 10

Ω or less.

For optimal performance, buffer the reference through

an op amp and bypass REF with a 10µF capacitor.

Consider the MAX1179/MAX1187/MAX1189’s equivalent

input noise (0.6LSB) when choosing a reference.

Reading the Conversion Result

EOC flags the microprocessor when a conversion is

complete. The falling edge of EOC signals that the data

is valid and ready to be output to the bus. D0–D15 are

the parallel outputs of the MAX1179/MAX1187/

MAX1189. These three-state outputs allow for direct

connection to a microcontroller I/O bus. The outputs

remain high-impedance during acquisition and conver-

sion. Data is loaded onto the bus with the third falling

forces the output bus back to high impedance. The

MAX1179/MAX1187/MAX1189 then wait for the next

falling edge of CS to start the next conversion cycle

(see Figure 2).

16-Bit, 135ksps, Single-Supply ADCs with

Bipolar Analog Input Range

10

______________________________________________________________________________________

Figure 6. Selecting Shutdown Mode

CS

EOC

REF &

BUFFER

POWER

ACQUISITION

CONVERSION

DATA

OUT

R/C

Figure 7. MAX1179/MAX1187/MAX1189 Reference Adjust

Circuit

MAX1179

MAX1187

MAX1189

REFADJ

+5V

68k

Ω

100k

Ω

150k

Ω

0.1

µF