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M29DW640D90ZA6E Datasheet(PDF) 6 Page - STMicroelectronics |
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M29DW640D90ZA6E Datasheet(HTML) 6 Page - STMicroelectronics |
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6 / 55 page  M29DW640D 6/56 SUMMARY DESCRIPTION The M29DW640D is a 64 Mbit (8Mb x8 or 4Mb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be per- formed using a single low voltage (2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode. The device features an asymmetrical block archi- tecture, with 16 parameter and 126 main blocks, divided into four Banks, A, B, C and D, providing multiple Bank operations. While programming or erasing is underway in one group of banks (from 1 to 3), reading can be conducted in any of the other banks. The bank architecture is summarized in Ta- ble 2. Eight of the Parameter Blocks are at the top of the memory address space, and eight are at the bottom. The M29DW640D has one extra 256 Byte block (Extended Block) that can be accessed using a dedicated command. The Extended Block can be protected and so is useful for storing security infor- mation. However the protection is irreversible, once protected the protection cannot be undone. Each block can be erased independently, so it is possible to preserve valid data while old data is erased. The blocks can be protected to prevent accidental Program or Erase commands from modifying the memory. Program and Erase com- mands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special op- erations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identi- fied. The command set required to control the memory is consistent with JEDEC standards. Chip Enable, Output Enable and Write Enable sig- nals control the bus operation of the memory. They allow simple connection to most micropro- cessors, often without additional logic. The memory is offered in TSOP48 (12x20mm) and TFBGA63 (7x11mm, 0.8mm pitch) packages. The memory is supplied with all the bits erased (set to ’1’). Figure 2. Logic Diagram Table 1. Signal Names AI06877b 22 A0-A21 W DQ0-DQ14 VCC M29DW640D E VSS 15 G RP DQ15A–1 RB VPP/WP BYTE A0-A21 Address Inputs DQ0-DQ7 Data Inputs/Outputs DQ8-DQ14 Data Inputs/Outputs DQ15A–1 Data Input/Output or Address Input E Chip Enable G Output Enable W Write Enable RP Reset/Block Temporary Unprotect RB Ready/Busy Output BYTE Byte/Word Organization Select VCC Supply Voltage VPP/WP VPP/Write Protect VSS Ground NC Not Connected Internally |
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