Digital Inputs

The digital inputs are compatible with CMOS logic.

Supply current increases slightly when toggling the

logic inputs through the transition zone between

Microprocessor Interfacing

The MAX5222 serial interface is compatible with

MICROWIRE, SPI, and QSPI. For SPI, clear the CPOL

and CPHA bits (CPOL = 0 and CPHA = 0). CPOL = 0

sets the inactive clock state to zero, and CPHA = 0

changes data at the falling edge of SCLK. This setting

allows SPI to run at full clock speeds. If a serial port is

not available on your µP, 3 bits of a parallel port can be

used to emulate a serial port by bit manipulation.

Minimize digital feedthrough at the voltage outputs by

operating the serial clock only when necessary.

Dual, 8-Bit, Voltage-Output

Serial DAC in 8-Pin SOT23

10

______________________________________________________________________________________

1LSB

REF

2

REF

1

256

ANALOG OUTPUT

REF

D

256

8

=×

=

×









=×









−

Table 4. Code Table

CS

SCLK

DIN

Figure 3. Detailed Serial-Interface Timing Diagram

0V

0

0

0

0

0

0

0

0

+× 







REF

1

256

1

0

0

0

0

0

0

0

+× 







REF

127

256

1

1

1

1

1

1

1

0

+×









=+

REF

128

256

REF

2

0

0

0

0

0

0

0

1

+×









REF

129

256

1

0

0

0

0

0

0

1

+× 







REF

255

256

1

1

1

1

1

1

1

1

ANALOG

OUTPUT

B0

B1

B2

B3

B4

B5

B6

B7

DAC CONTENTS

Note:

where D = decimal

value of digital input