TRF4900

SINGLECHIP RF TRANSMITTER

SLWS092G − JULY 2000 − REVISED FEBRUARY 2005

9

POST OFFICE BOX 655303

TRF4900 direct digital synthesizer implementation (continued)

The frequency of the reference oscillator,

maximum DDS output frequency. Together with the accumulator width (in bits), the frequency resolution of the

DDS can be calculated. Multiplied by the divider ratio (prescaler) of the PLL, N, the minimum frequency step

size of the TRF4900 is calculated as follows:

Dƒ + N

ƒ

ref

The 24-bit accumulator can be programmed via two 22-bit frequency setting registers (the A-word determines

the mode0 frequency, the B-word determines the mode1 frequency) with the two MSB bits set to 0.

Consequently, the maximum bit weight of the DDS system is reduced to 1/8 (see Figure 6). This bit weight

corresponds to a VCO output frequency of (

level, the internal mode select logic loads the frequency register with either the DDS_0 or DDS_1 frequency

(see Figure 5 and Figure 6).

DDS Frequency Setting For Mode0/1

From A-Word/B-Word

22

0

0 X X . . . .

. . . XX XX X

MSB

LSB

23 22 21

20 . . .

. . . 4

3

2

1

0

MSB

23 22

DDS Frequency Register

8

FSK Frequency Deviation Register − DEV

00

. . . .

X0 0

XX X X X X X

LSB

9

8 7 6

5

4

3

2

1

0

. . . .

DDS Frequency Register

. . . .

. . . .

. . . 1

2 24

Figure 6. Implementation of the DDS Frequency and FSK Frequency

Deviation in the DDS Frequency Register

The VCO output frequency,

or DDS_1 in the B-word), can be calculated as follows:

ƒ

N

ƒ

ref

+ N

ƒ

ref

DDS_x

If FSK modulation is selected (MM=0; C-Word, bit 16), then the 8-bit FSK deviation register can be used to

program the frequency deviation of the 2-FSK modulation. Figure 6 illustrates where the 8 bits of the FSK

deviation register map into the 24-bit DDS frequency register. Since the two LSBs are set to 0, the total FSK

deviation can be determined as follows:

Dƒ

DEV

ƒ

ref

Hence, the 2-FSK frequency, set by the level on the TX_DATA is calculated as follows:

ƒ

out1:TX_DATA

ƒ

ref

DDS_x

ƒ

out2:TX_DATA

ƒ

ref

(DDS_x

) 4

DEV)

This frequency modulated output signal is used as a reference input signal for the PLL circuit. Channel width

(frequency deviation) for 2-FSK modulation and channel spacing are software programmable. The minimum

channel width and minimum channel spacing depend on the RF system frequency plan.