TRF4900

SINGLECHIP RF TRANSMITTER

SLWS092G − JULY 2000 − REVISED FEBRUARY 2005

6

POST OFFICE BOX 655303

direct digital synthesizer (DDS)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Reference oscillator input frequency,

ƒref

As oscillator

15

26

MHz

Reference oscillator input frequency,

ƒref

As buffer

15

26

MHz

Programmable DDS divider ratio

22 bits

0

4194303

DDS divider resolution,

∆ƒ

N

× ƒref ÷ 224

FSK − modulation register ratio

8 bits

0

1020

FSK − modulation resolution

N

× ƒref ÷ 222

PLL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

RF input frequency

850

950

MHz

RF input power

Internal VCO bypassed; external input applied to VCO_TANK2

−10

dBm

RF input divider ratio, N

256

512

RF output frequency resolution

N

× ƒref ÷ 224

Charge pump current

Programmable with external resistor, 100 k

Ω nominal, APLL = 0

70

µA

power amplifier

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Frequency range

850

950

MHz

0-dB attenuation

7

Amplifier output power (see Note 2)

10-dB attenuation

−3

dBm

Amplifier output power (see Note 2)

20-dB attenuation

−12

dBm

Amplifier off

−52

Optimal load impedance

See Figure 11

Ω

2nd-order harmonic

VCC = 3 V, 0-dB attenuation

−13

dBc

3rd-order harmonic

VCC = 3 V, 0-dB attenuation

−32

dBc

NOTE 2: The device and output matching network (see Application Information section) is designed to provide the output power into a 50-

Ω load.

The device stability was tested (no parasitic oscillations) with an output VSWR of 10:1 over all phase angles and is not tested in

production.

typical mode switching and lock times

OPERATION

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Standby to transmit time†

From rising edge of STDBY to valid RF signal at PA_OUT, APLL = 111b

(maximum)

500

µs

† Highly dependent upon loop filter topology