DP7411

Doc. No. MD-2114 Rev. J

2

© NIDEC COPAL ELECTRONICS CORP.

Characteristics subject to change without notice

PIN DESCRIPTIONS

SI: Serial Input

SI is the serial data input pin. This pin is used to input all

opcodes, byte addresses and data to be written to the

DP7411. Input data is latched on the rising edge of the

serial clock.

SO: Serial Output

SO is the serial data output pin. This pin is used to transfer

data out of the DP7411. During a read cycle, data is

shifted out on the falling edge of the serial clock.

SCK: Serial Clock

SCK is the serial clock pin. This pin is used to synchronize

the communication between the microcontroller and the

DP7411. Opcodes, byte addresses or data present on

the SI pin are latched on the rising edge of the SCK. Data

on the SO pin is updated on the falling edge of the SCK.

A0, A1: Device Address Inputs

These inputs set the device address when addressing

multiple devices. A total of four devices can be addressed

on a single bus. A match in the slave address must be

made

with

the

address

input

in

order

to

initiate

communication with the DP7411.

terminal connections on a mechanical potentiometer.

mechanical potentiometer.

CS

¯¯¯: Chip Select

DP7251 and CS

¯¯¯ high disables the DP7411. CS

¯¯¯ high

takes the SO output pin to high impedance and forces the

devices into a Standby mode (unless an internal write

operation is underway). The DP7411 draws ZERO

current in the Standby mode. A high to low transition on

CS

¯¯¯ is required prior to any sequence being initiated. A low

to high transition on CS

¯¯¯ after a valid write sequence is

what initiates an internal write cycle.

WP

¯¯¯: Write Protect

WP

¯¯¯ is the Write Protect pin. The Write Protect pin will

allow normal read/write operations when held high.

When WP

¯¯¯ is tied low, all non-volatile write operations to

the Data registers are inhibited (change of wiper control

register is allowed). WP

¯¯¯ going low while CS

¯¯¯ is still low will

interrupt a write to the registers. If the internal write cycle

has already been initiated, WP

¯¯¯ going low will have no

effect on any write operation.

HOLD

¯¯¯¯¯: Hold

The HOLD

¯¯¯¯¯ pin is used to pause transmission to the

DP7411 while in the middle of a serial sequence without

having to re-transmit entire sequence at a later time. To

pause, HOLD

¯¯¯¯¯ must be brought low while SCK is low. The

SO pin is in a high impedance state during the time the part

is paused, and transitions on the SI pins will be ignored. To

resume communication, HOLD

¯¯¯¯¯ is brought high, while SCK

is low. (HOLD

¯¯¯¯¯ should be held high any time this function is

not being used.) HOLD

Pin

SOIC

Pin

TSSOP

Name

Function

119

Supply Voltage

220

Low Reference Terminal for

Potentiometer 0

321

High Reference Terminal for

Potentiometer 0

422

Wiper Terminal for

Potentiometer 0

523

CS

¯¯¯

Chip Select

624

WP

¯¯¯

Write Protection

7

1

SI

Serial Input

82

Device Address

93

Low Reference Terminal for

Potentiometer 1

10

4

High Reference Terminal for

Potentiometer 1

11

5

Wiper Terminal for

Potentiometer 1

12

6

GND

Ground

13

7

NC

No Connect

14

8

NC

No Connect

15

9

NC

No Connect

16

10

NC

No Connect

17

11

SCK

Bus Serial Clock

18

12

HOLD

¯¯¯¯¯

Hold

19

13

SO

Serial Data Output

20

14

Device Address, LSB

21

15

NC

No Connect

22

16

NC

No Connect

23

17

NC

No Connect

24

18

NC

No Connect